US5696768A
Expired / Lapsed
US
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Method and apparatus for data storage array tracking
Assignee: Intel Corp
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Filing: 1996-12-10
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Granted: 1997-12-09
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Expires: 2016-12-10
Abstract
Abstract A data storage array is provided having a number, n, of sequential data storage areas for the storage of data. A valid status array including n bits is provided where there is a one to one correspondence between the bits of the valid status array and the data storage areas of the data storage array. When valid data are written into a data storage area, the status bit of the valid status array corresponding to this data storage area is set to indicate that valid data are present. When data are read out of the data storage area, the corresponding status bit is cleared indicating the absence of valid data. If the data storage array is one that is written to in a random access manner and read from sequentially, as a queue, then the valid status array would indicate the presence of valid data at the head of the queue for the data storage array.
Inventors
- 👤 David J. Harriman
- 👤 Aditya Sreenivas
- 👤 Russell W. Dyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:16
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
99 words
A data storage array status tracking apparatus comprising: a data storage array including n data storage areas capable of storing data where data are written to the data storage areas of said data storage array in a random access manner and data are read sequentially from the data storage areas of said data storage array; and a valid status array storing n status bits, where there is a one-to-one correspondence between said status bits and the data storage areas of said data storage array, each status bit indicating whether valid data are contained in its corresponding data storage area.
Claim 2
Dependent Claim
99 words
A data storage array status tracking apparatus comprising: a data storage array including n data storage areas capable of storing data where data are written to the data storage areas of said data storage array in a random access manner and data are read sequentially from the data storage areas of said data storage array; and a valid status array storing n status bits, where there is a one-to-one correspondence between said status bits and the data storage areas of said data storage array, each status bit indicating whether valid data are contained in its corresponding data storage area.
Claim 3
Dependent Claim
57 words
The apparatus of claim 1 wherein when data are written to a first one of the data storage areas of said data storage array, a first one of said status bits corresponding to said first one of the data storage areas is set to indicate that said first one of the data storage areas contains valid data.
Claim 4
Dependent Claim
59 words
The apparatus of claim 2 wherein when data are read from the first one of the data storage areas of said data storage array, the first one of said status bits corresponding to said first one of the data storage areas is cleared to indicate that said first one of the data storage areas does not contain valid data.
Claim 5
Dependent Claim
44 words
The apparatus of claim 1 further comprising: a logic circuit having a plurality of inputs coupled to said valid status array and at least one output, said logic circuit indicating a number of data storage areas in said data storage array containing valid data.
Claim 6
Dependent Claim
44 words
The apparatus of claim 3 further comprising: a logic circuit having a plurality of inputs coupled to said valid status array and at least one output, said logic circuit indicating a number of data storage areas in said data storage array containing valid data.
Claim 7
Dependent Claim
40 words
The apparatus of claim 1 wherein said valid status array is a shift register, where a most significant status bit of said valid status array corresponds to a next data storage area to be read from said data storage array.
Claim 8
Dependent Claim
40 words
The apparatus of claim 3 wherein said valid status array is a shift register, where a most significant status bit of said valid status array corresponds to a next data storage area to be read from said data storage array.
Claim 9
Dependent Claim
40 words
The apparatus of claim 4 wherein said valid status array is a shift register, where a most significant status bit of said valid status array corresponds to a next data storage area to be read from said data storage array.
Claim 10
Independent Claim
141 words
A method of tracking a status of a data storage array including a plurality of data storage areas where data are written to the data storage array in a random access manner and data are read from the data storage array sequentially, the method comprising: (a) storing data in a first data storage areas of said data storage array; (b) setting a first status bit in a valid status array storing n status bits, where there is a one-to-one correspondence between said status bits and the data storage areas of said data storage array and said first status bit corresponds to said first data storage area, such that each of said status bits indicates whether valid data are contained in its corresponding data storage area; and (c) reading data out of the first data storage area of said data storage array.
Claim 11
Independent Claim
141 words
A method of tracking a status of a data storage array including a plurality of data storage areas where data are written to the data storage array in a random access manner and data are read from the data storage array sequentially, the method comprising: (a) storing data in a first data storage areas of said data storage array; (b) setting a first status bit in a valid status array storing n status bits, where there is a one-to-one correspondence between said status bits and the data storage areas of said data storage array and said first status bit corresponds to said first data storage area, such that each of said status bits indicates whether valid data are contained in its corresponding data storage area; and (c) reading data out of the first data storage area of said data storage array.
Claim 12
Dependent Claim
34 words
The method of claim 9 further comprising: (d) clearing said first status bit in said valid status array to indicate that said first one of the data storage areas does not contain valid data.
Claim 13
Dependent Claim
36 words
The method of claim 10 wherein the data storage areas of the data storage array are in a sequential order and data are sequentially read out of the data storage areas of the data storage array.
Claim 14
Dependent Claim
46 words
The method of claim 9 further comprising: (d) generating an indication of a number of data storage areas in said data storage array containing valid data at at least one output of a logic circuit having a plurality of inputs coupled to the valid status array.
Claim 15
Dependent Claim
46 words
The method of claim 10 further comprising: (e) generating an indication of a number of data storage areas in said data storage array containing valid data at at least one output of a logic circuit having a plurality of inputs coupled to the valid status array.
Claim 16
Dependent Claim
46 words
The method of claim 11 further comprising: (e) generating an indication of a number of data storage areas in said data storage array containing valid data at at least one output of a logic circuit having a plurality of inputs coupled to the valid status array.
Claim 17
Dependent Claim
79 words
The method of claim 11 wherein said valid status array is a shift register, and a most significant status bit of said valid status array corresponds to a next data storage area to be read from said data storage array, the method further comprising: (e) shifting said shift register one bit place, such that the most significant status bit of said valid status array corresponds to the next data storage area to be read from said data storage array.
Claim 18
Dependent Claim
79 words
The method of claim 14 wherein said valid status array is a shift register, and a most significant status bit of said valid status array corresponds to a next data storage area to be read from said data storage array, the method further comprising: (f) shifting said shift register one bit place, such that the most significant status bit of said valid status array corresponds to the next data storage area to be read from said data storage array.
Claim 19
Independent Claim
160 words
An apparatus for tracking status of a data storage array in an Advanced Graphics Port (A.G.P.) Interface comprising: an A.G.P. target component having a read data return queue including: a data storage array including n data storage areas capable of storing data, where data are written to the data storage areas of said data storage array in a random access manner and data are read sequentially from the data storage areas of said data storage array; and a valid status array storing n status bits, where there is a one-to-one correspondence between said status bits and the data storage areas of said data storage array, where each status bit indicates whether valid data are contained in its corresponding data storage area; and an A.G.P. master component coupled to the read data return queue of said A.G.P. target component via an A.G.P. interface, said A.G.P. master component capable of receiving data stored in said data storage array via said A.G.P. interface.
Claim 20
Independent Claim
160 words
An apparatus for tracking status of a data storage array in an Advanced Graphics Port (A.G.P.) Interface comprising: an A.G.P. target component having a read data return queue including: a data storage array including n data storage areas capable of storing data, where data are written to the data storage areas of said data storage array in a random access manner and data are read sequentially from the data storage areas of said data storage array; and a valid status array storing n status bits, where there is a one-to-one correspondence between said status bits and the data storage areas of said data storage array, where each status bit indicates whether valid data are contained in its corresponding data storage area; and an A.G.P. master component coupled to the read data return queue of said A.G.P. target component via an A.G.P. interface, said A.G.P. master component capable of receiving data stored in said data storage array via said A.G.P. interface.
Claim 21
Dependent Claim
57 words
The apparatus of claim 17 wherein when data are written to a first one of the data storage areas of said data storage array, a first one of said status bits corresponding to said first one of the data storage areas is set to indicate that said first one of the data storage areas contains valid data.
Claim 22
Dependent Claim
59 words
The apparatus of claim 18 wherein when data are read from the first one of the data storage area of said data storage array, the first one of said status bits corresponding to said first one of the data storage areas is cleared to indicate that said first one of the data storage areas does not contain valid data.
Claim 23
Dependent Claim
50 words
The apparatus of claim 19 where the read data return queue further comprises: a logic circuit having a plurality of inputs coupled to said valid status array and at least one output, said logic circuit indicating a number of data storage areas in said data storage array containing valid data.
Claim 24
Dependent Claim
40 words
The apparatus of claim 20 wherein said valid status array is a shift register, where a most significant status bit of said valid status array corresponds to a next data storage area to be read from said data storage array.
References Cited (Backward Citations)
US5592648A
Cited
US5218680A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-08 | 2009-06-09 | 2009-12-09 | $7700.00 | Window Closed / Lapsed |