US5694553A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for determining the dispatch readiness of buffered load operations in a processor
Assignee: Intel Corp
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Filing: 1995-07-27
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Granted: 1997-12-02
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Expires: 2015-07-27
Abstract
Abstract The present invention provides a buffer management scheme for load operations that permits load operations to be stored for execution to memory. The buffer management scheme of the present invention calculates the readiness of multiple buffered load operations to speed up dispatch of at least one of the load operations to memory. By providing such management, the present invention allows memory operations and their execution by a device, such as a processor, to be coordinated with the operation of the system and other operations in the processor.
Inventors
- 👤 Jeffrey M. Abramson
- 👤 Kris G. Konigsfeld
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:00
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824; G06F9/383; G06F9/30003; G06F9/3004; G06F9/30043; G06F9/3802; G06F9/3816; G06F9/3834; G06F9/3836; G06F9/3842; G06F9/3854; G06F9/3856; G06F9/3858
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
105 words
A processor for use in a system, said processor comprising: a bus; an issue unit coupled to the bus to issue operations including load operations in response to instructions fetched from memory; an array coupled to the issue unit having entries to store a predetermined number of load operations prior to dispatch to memory for execution; an array management mechanism coupled to the array, wherein the array management mechanism determines dispatch readiness of load operations stored in the array prior to reading out one load operation and generates an indication of the dispatch readiness of said one load operation for use in arbitration for dispatch.
Claim 2
Dependent Claim
105 words
A processor for use in a system, said processor comprising: a bus; an issue unit coupled to the bus to issue operations including load operations in response to instructions fetched from memory; an array coupled to the issue unit having entries to store a predetermined number of load operations prior to dispatch to memory for execution; an array management mechanism coupled to the array, wherein the array management mechanism determines dispatch readiness of load operations stored in the array prior to reading out one load operation and generates an indication of the dispatch readiness of said one load operation for use in arbitration for dispatch.
Claim 3
Dependent Claim
29 words
The processor defined in claim 1 wherein the array management mechanism generates the indication by ORing together a ready indication of each of the predetermined number of load operations.
Claim 4
Dependent Claim
28 words
The processor defined in claim 1 array management mechanism further comprises a wired-OR circuit driven by readiness indications associated with each of the predetermined number of load operations.
Claim 5
Dependent Claim
27 words
The processor defined in claim 1 wherein readiness of each load operation is based on validity of said each load operation and execution completeness within the processor.
Claim 6
Dependent Claim
205 words
A processor for use in a system, said processor comprising: a bus; an issue unit coupled to the bus to issue operations including load operations in response to instructions fetched from memory; an array coupled to the issue unit having entries to store a predetermined number of load operations prior to dispatch to memory for execution; an array management mechanism coupled to the array, wherein the array management mechanism determines dispatch readiness of load operations stored in the array prior to reading out one load operation and generates an indication of the dispatch readiness of said one load operation; a scheduler coupled to the array management mechanism to schedule a load operation stored in the array for dispatch to memory for execution, when the scheduler receives readiness indications from each load buffer entry; an arbitration mechanism arbitrating among a plurality of requests and generating an indication to select one of the plurality of requests for dispatch, wherein the arbitration mechanism generates a select signal indicative of selection; and a dispatch mechanism coupled to the arbitration mechanism and the array having a plurality of sources of operations, wherein the dispatch mechanism dispatches operations from one of the plurality of sources in response to the select signal.
Claim 7
Dependent Claim
205 words
A processor for use in a system, said processor comprising: a bus; an issue unit coupled to the bus to issue operations including load operations in response to instructions fetched from memory; an array coupled to the issue unit having entries to store a predetermined number of load operations prior to dispatch to memory for execution; an array management mechanism coupled to the array, wherein the array management mechanism determines dispatch readiness of load operations stored in the array prior to reading out one load operation and generates an indication of the dispatch readiness of said one load operation; a scheduler coupled to the array management mechanism to schedule a load operation stored in the array for dispatch to memory for execution, when the scheduler receives readiness indications from each load buffer entry; an arbitration mechanism arbitrating among a plurality of requests and generating an indication to select one of the plurality of requests for dispatch, wherein the arbitration mechanism generates a select signal indicative of selection; and a dispatch mechanism coupled to the arbitration mechanism and the array having a plurality of sources of operations, wherein the dispatch mechanism dispatches operations from one of the plurality of sources in response to the select signal.
Claim 8
Dependent Claim
23 words
The processor defined in claim 5 wherein generation of the array ready signal is performed in parallel with scheduling operation by the scheduler.
Claim 9
Dependent Claim
29 words
The processor defined in claim 5 wherein the array management mechanism generates the indication by ORing together a ready indication of each of the predetermined number of load operations.
Claim 10
Dependent Claim
28 words
The processor defined in claim 5 array management mechanism further comprises a wired-OR circuit driven by readiness indications associated with each of the predetermined number of load operations.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-01 | 2001-06-02 | 2001-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-01 | 2005-06-02 | 2005-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-01 | 2009-06-02 | 2009-12-02 | $7700.00 | Window Closed / Lapsed |