Computer system with double simultaneous displays showing differing display images

Claim 1

A system comprising: an input device for receiving inputs from a user of said system; a central processing unit (CPU) interfacing with said input device and responding to said inputs by performing a processing function producing an output including display data; an output device receiving said output response from said CPU and providing a sensible output response; said output device including at least a pair of display devices each providing a different visible image to the user in response to said display data; a video display controller (VDC) including a display data processing circuit (DDPC); a dynamic random access memory (DRAM) interfacing with said CPU via said VDC and receiving said display data for temporary storage; said VDC including at least a pair of display first-in-first-out (FIFO) memories interfacing with said DRAM for receiving and temporarily holding display data to be imminently presented on a corresponding one of said at least a pair of display devices, said at least a pair of display FIFO's also interfacing with said DDPC to provide thereto corresponding data destined for each particular one of said at least a pair of display devices, said DDPC including plural display data decode and over scan (DDOS) portions each corresponding to one of said at least a pair of display FIFO's and receiving said display data therefrom, each of said plural DDOS portions providing a corresponding demultiplexer circuit receiving said display data in a first bit-word format and responsively providing a data bit stream in a selected second bit-word format to a corresponding one of said at least a pair of display devices; a counter for counting a number of words in said second bit-word format that have been demultiplexed from each word in said first bit-word format, and means for generating a data request signal when all words of data in said second bit-word format have been demultiplexed from a word in said first bit-word format.

Claim 2

A system comprising: an input device for receiving inputs from a user of said system; a central processing unit (CPU) interfacing with said input device and responding to said inputs by performing a processing function producing an output including display data; an output device receiving said output response from said CPU and providing a sensible output response; said output device including at least a pair of display devices each providing a different visible image to the user in response to said display data; a video display controller (VDC) including a display data processing circuit (DDPC); a dynamic random access memory (DRAM) interfacing with said CPU via said VDC and receiving said display data for temporary storage; said VDC including at least a pair of display first-in-first-out (FIFO) memories interfacing with said DRAM for receiving and temporarily holding display data to be imminently presented on a corresponding one of said at least a pair of display devices, said at least a pair of display FIFO's also interfacing with said DDPC to provide thereto corresponding data destined for each particular one of said at least a pair of display devices, said DDPC including plural display data decode and over scan (DDOS) portions each corresponding to one of said at least a pair of display FIFO's and receiving said display data therefrom, each of said plural DDOS portions providing a corresponding demultiplexer circuit receiving said display data in a first bit-word format and responsively providing a data bit stream in a selected second bit-word format to a corresponding one of said at least a pair of display devices; a counter for counting a number of words in said second bit-word format that have been demultiplexed from each word in said first bit-word format, and means for generating a data request signal when all words of data in said second bit-word format have been demultiplexed from a word in said first bit-word format.

Claim 12

A system as in claim. 2, in which the first and second converter means each comprise a variably configurable data decode and over scan site (DDOS) means.

Claim 23

A method for displaying video data, comprising the steps of: (a) providing first and second video display means; (b) storing first and second video data corresponding to first and second images for display on the first and second video display means respectively in a memory means, the first and second video data being in a first format; (c) reading the first and second video data out of the memory means; (d) converting the first and second video data from the first format into first and second display data in second and third formats respectively; and (e) applying the first and second display data to the first and second video display means respectively; and wherein step (d) comprises sequentially demultiplexing words of the first display data from each word of the first video data; and step (d) comprises the substeps of: (d1) counting a number of words of the first display data that are demultiplexed from each word of the first video data, (d2) generating a data request signal when all words of the first display data have been demultiplexed from a word of first video data.

Claim 24

A method for displaying video data, comprising the steps of: (a) providing first and second video display means; (b) storing first and second video data corresponding to first and second images for display on the first and second video display means respectively in a memory means, the first and second video data being in a first format; (c) reading the first and second video data out of the memory means; (d) converting the first and second video data from the first format into first and second display data in second and third formats respectively; and (e) applying the first and second display data to the first and second video display means respectively; and wherein step (d) comprises sequentially demultiplexing words of the first display data from each word of the first video data; and step (d) comprises the substeps of: (d1) counting a number of words of the first display data that are demultiplexed from each word of the first video data, (d2) generating a data request signal when all words of the first display data have been demultiplexed from a word of first video data.