Integrated drivers for flat panel displays employing chalcogenide logic elements

Claim 2

A logic operational circuit comprising: a least one logic gate wherein each logic gate comprises: a first chalcogenide threshold switch connected at one end to an activation point and at the other end to a second chalcogenide threshold switch; at least one input resistor, each input resistor connected at one end between said first and second threshold switches and at the other end to a unique input point; a third threshold switch connected at one end to said second threshold switch at a terminal opposite that of a junction of said first and second threshold switches, said third threshold switch connected at the other end to a reset point; and an output point connected between said second and said third threshold switches.

Claim 3

The logic operational circuit of claim 1, wherein said circuit employs multi-phase clocking.

Claim 4

The logic operational circuit of claim 2, wherein said multi-phase clocking is three-phase clocking.

Claim 5

The logic operational circuit of claim 2, wherein said multi-phase clocking is four-phase clocking.

Claim 6

The logic operational circuit of claim 4, wherein said four-phase clocking employs a fifty percent duty cycle.

Claim 7

The logic operational circuit of claim 1, wherein said at least one input resistor is a single input resistor connected at one end to a unique input point and at the other end between said first and second chalcogenide switches.

Claim 8

A display driver for driving a flat panel display having rows and columns, said display driver comprising: row driver means for activating said rows of said flat panel display; and column driver means for setting pixel intensity values for each of said activated rows; wherein said row driver means and said column driver means each comprise a plurality of logic gates where each logic gate comprises: a first and a second chalcogenide threshold switch connected in series; and at least one input resistor, each input resistor connected at one end to a point between said first and said second threshold switches and at the other end to a unique one of at least one input point.

Claim 9

A display driver for driving a flat panel display having rows and columns, said display driver comprising: row driver means for activating said rows of said flat panel display; and column driver means for setting pixel intensity values for each of said activated rows; wherein said row driver means and said column driver means each comprise a plurality of logic gates where each logic gate comprises: a first and a second chalcogenide threshold switch connected in series; and at least one input resistor, each input resistor connected at one end to a point between said first and said second threshold switches and at the other end to a unique one of at least one input point.

Claim 10

The display driver of claim 7, wherein each of said plurality of logic gates includes one or more logic gates selected from the group consisting of INVERTER, IMPROVED-INVERTER, NOR, IMPROVED-NOR and combinations thereof, wherein said INVERTER comprises: a first chalcogenide threshold switch connected at one end to a second chalcogenide threshold switch and at the other end to an activation point; an input resistor connected at one end to a point between said first and said second threshold switches and at the other end to a unique input point; a ground resistor connected at one end to said second threshold switch at a terminal opposite that of a junction of said first and said second threshold switches, said ground resistor connected at the other end to ground; and an output point connected between said second threshold switch and said ground resistor; said IMPROVED-INVERTER comprises: a first chalcogenide threshold switch connected at one end to a second chalcogenide threshold switch and at the other end to an activation point; an input resistor connected at one end to a point between said first and said second threshold switches and at the other end to a unique input point; a third threshold switch connected at one end to said second threshold switch at a terminal opposite a junction between said first and said second threshold switches and at the other end to a reset point; and an output point connected between said second and said third threshold switches; said NOR comprises: a first chalcogenide threshold switch connected at one end to a second chalcogenide threshold switch and at the other end to an activation point; a plurality of input resistors, each connected at one end to a point between said first and said second threshold switches and at the other end to a unique one of a plurality of input points; a ground resistor connected at one end to said second threshold switch at a terminal opposite that of a junction of said first and said second threshold switches, said ground resistor connected at the other end to ground; and an output point connected between said second threshold switch and said ground resistor; said IMPROVED-NOR comprises: a first chalcogenide threshold switch connected at one end to a second chalcogenide threshold switch and at the other end to an activation point; a plurality of input resistors, each connected at one end to a point between said first and said second threshold switches and at the other end to a unique one of a plurality of input points; a third threshold switch connected at one end to said second threshold switch at a terminal opposite a junction between said first and said second threshold switches and at the other end to a reset point; and an output point connected between said second and said third threshold switches.

Claim 11

The display driver of claim 8, wherein said plurality of logic gates employ multi-phase clocking.

Claim 12

The display driver of claim 9, wherein said multi-phase clocking is three-phase clocking.

Claim 13

The display driver of claim 9, wherein said multi-phase clocking is four-phase clocking.

Claim 14

The display driver of claim 11, wherein said four-phase clocking has a fifty percent duty cycle.

Claim 15

The display driver of claim 7, wherein said row driver means comprises: row shifting means for shifting a sequence of row activation data that controls the activation of said rows; and row driving means for activating said rows.

Claim 16

The display driver of claim 7, wherein said column driver means comprises: column shifting means for shifting a sequence of digital pixel intensity data; decoder means for converting said digital pixel intensity data into a digital decoder output signal; and digital conversion means for converting said digital decoder output signal into analog pixel intensity data.

Claim 17

The display driver of claim 13, wherein said row shifting means comprises: a connected sequence of INVERTER's wherein said output point of one INVERTER is connected to a unique input point of the next INVERTER in said connected sequence; a row shifter input point connected to the first INVERTOR in said connected sequence.

Claim 18

The display driver of claim 13, wherein said row driving means comprises: at least one IMPROVED-INVERTER, wherein the activation point of each IMPROVED-INVERTER is connected to a common activation point, and the reset point of each IMPROVED-INVERTER is connected to a common reset point.

Claim 19

The display driver of claim 14, wherein said column shifting means comprises: a connected sequence of INVERTER's wherein said output point of one INVERTER is connected to a unique input point of the next INVERTER in said connected sequence; and a column shifter input point connected to the first INVERTER in said connected sequence.

Claim 20

The display driver of claim 14, wherein said decoder means comprises: a plurality of NOR's wherein said activation point of each of said plurality of NOR's is connected to a common activation point.

Claim 21

The display driver of claim 14, wherein said digital conversion means comprises: a plurality of logic gates wherein each logic gate comprises: a first chalcogenide threshold switch connected at one end to a second chalcogenide threshold switch and at the other end to an analog voltage point; and an input resistor connected at one end to a point between said first and said second threshold switches, and at other end to an input point; a common digital-to-analog output point connected to said second threshold switch of each of said plurality of logic gates at a terminal opposite a junction of said first and said second threshold switches; and a clocking resistor connected at one end to said common digital-to-analog output point and at the other end to an activation point.