US5691910A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Generic gate level model for characterization of glitch power in logic cells
Assignee: Bell Semiconductor LLC
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Filing: 1996-06-10
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Granted: 1997-11-25
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Expires: 2016-06-10
Abstract
Abstract According to the present invention, there is provided a method for determining glitch power in a logic circuit having a power supply terminal, a first input, a second input, and an output coupled to a capacitive load. In one embodiment, the method includes: determining at least one ramp time sum, each ramp time sum corresponding to a pair of ramp times; determining a plurality of separation times by: selecting a minimum separation time, selecting a maximum separation time, dividing a difference between the minimum separation time and the maximum separation by a step value to determine a separation time increment, incrementing the minimum separation time by multiples of the separation time increment until the incremented minimum separation time approximately equals the maximum separation time; determining an average current flowing through the power supply terminal for each separation time and ramp time sum; storing the average current in a computer-readable medium; and interpolating an actual average current from the stored average current values based upon actual ramp times and an actual separation time.
Inventors
- 👤 John A. Thodiyil
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:22
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F2119/00; G06F2119/06
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
161 words
A method for determining glitch power in a logic circuit having a power supply terminal, a first input, a second input, and an output coupled to a capacitive load, the method comprising: determining at least one ramp time sum, each ramp time sum corresponding to a pair of ramp times; determining a plurality of separation times by: selecting a minimum separation time, selecting a maximum separation time, dividing a difference between the minimum separation time and the maximum separation by a step value to determine a separation time increment, incrementing the minimum separation time by multiples of the separation time increment until the incremented minimum separation time approximately equals the maximum separation time; determining an average current flowing through the power supply terminal for each separation time and ramp time sum; storing the average current in a computer-readable medium; and interpolating an actual average current from the stored average current values based upon actual ramp times and an actual separation time.
Claim 2
Independent Claim
161 words
A method for determining glitch power in a logic circuit having a power supply terminal, a first input, a second input, and an output coupled to a capacitive load, the method comprising: determining at least one ramp time sum, each ramp time sum corresponding to a pair of ramp times; determining a plurality of separation times by: selecting a minimum separation time, selecting a maximum separation time, dividing a difference between the minimum separation time and the maximum separation by a step value to determine a separation time increment, incrementing the minimum separation time by multiples of the separation time increment until the incremented minimum separation time approximately equals the maximum separation time; determining an average current flowing through the power supply terminal for each separation time and ramp time sum; storing the average current in a computer-readable medium; and interpolating an actual average current from the stored average current values based upon actual ramp times and an actual separation time.
Claim 3
Dependent Claim
30 words
A method as in claim 1 wherein one of the ramp time pairs comprises a pair of equal ramp times, each ramp time being half of the ramp time sum.
Claim 4
Dependent Claim
23 words
A method as in claim 1 wherein one of the ramp time pairs comprises a minimum ramp time and a maximum ramp time.
Claim 5
Dependent Claim
103 words
A method as in claim 3 wherein selecting a minimum separation time comprises calculating the minimum separation time in accordance with the following expression: ts.sub.-- min=-1.0 (b.sub.-- to.sub.-- z(cload, tw.sub.-- Tr.sub.-- min)-a.sub.-- to.sub.-- z(cload, Tr.sub.-- min)+0.5(tw-Tr.sub.-- min)) where ts -- min represents the minimum separation time, tw represents the ramp time sum, Tr -- min represents the minimum ramp time, a -- to -- z represents the path delay time for a signal received at input a of the logic gate and b -- to -- z represents the path delay time for a signal received at input b of the logic gate.
Claim 6
Dependent Claim
102 words
A method as in claim 3 wherein selecting a maximum separation time comprises calculating the maximum separation time in accordance with the following expression: ts.sub.-- max=a.sub.-- to.sub.-- z(cload, tw-Tr.sub.-- min)-b.sub.-- to.sub.-- z(cload, Tr.sub.-- min)+0.5 (tw-Tr.sub.-- min) where ts -- max represents the maximum separation time, tw represents the ramp time sum, Tr -- min represents the minimum ramp time, a -- to -- z represents the path delay time for a signal received at input a of the logic gate and b -- to -- z represents the path delay time for a signal received at input b of the logic gate.
Claim 7
Dependent Claim
45 words
A method as in claim 1 wherein determining an average current flowing through the power supply terminal for each separation time comprises providing at least one of the ramp time pairs and the capacitive load to a computer encoded with an electronic circuit analysis program.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-24 | 2001-05-26 | 2001-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-24 | 2005-05-26 | 2005-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-24 | 2009-05-26 | 2009-11-25 | $7700.00 | Window Closed / Lapsed |