US5689689A
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US
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Clock circuits for synchronized processor systems having clock generator circuit with a voltage control oscillator producing a clock signal synchronous with a master clock signal
Assignee: Hewlett Packard Development Co LP
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Filing: 1995-06-07
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Granted: 1997-11-18
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Expires: 2015-06-07
Abstract
Abstract A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
Inventors
- 👤 Steven C. Meyers
- 👤 John Michael Brown
- 👤 William F. Bruckert
- 👤 James Stephens Klecka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:22
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31727; G06; G06F; G06F1/00; G06F1/04; G06F1/12; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/16; G06F11/1604; G06F11/1629; G06F11/1633; G06F11/1641; G06F11/1645; G06F11/165; G06F11/1658; G06F11/1675; G06F11/1679; G06F11/1687; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/14; G06F12/1458; G06F12/1483; H; H04; H04L; H04L47/00; H04L47/10; H04L49/00; H04L49/90; H04L49/901; H04L49/9057; H04L69/00; H04L69/40; G01R31/3181; G01R31/3185; G01R31/318533; G06F11/004; G06F11/1008; G06F11/1044; G06F11/1666; G06F11/167; G06F11/1683; G06F11/1695; G06F11/20; G06F11/202; G06F11/2043; G06F11/2097; G06F11/22; G06F11/26; G06F11/273; G06F11/2736; G06F2201/00; G06F2201/845; H04L12/00; H04L12/54; H04L12/56
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
193 words
Apparatus for providing clock signals synchronized to a master clock signal for at least a pair of synchronous processing elements, comprising: each of the pair of processing elements including: a master oscillator circuit to produce a clock signal, a clock generator circuit coupled to receive the master clock signal to produce the synchronized clock signals therefrom for such one of the pair of processing elements, the clock generator circuit having a voltage controlled oscillator circuit responsive to a phase voltage to produce a first clock signal that is synchronous with the master clock signal, a counter circuit coupled to receive the first clock signal to produce a number of divisions of the first clock signal that includes the synchronized clock signals and a replica of the master clock signal, and a phase compare means coupled to receive the master clock signal and the replica of the master clock signal to produce the phase voltage; and means for coupling the master oscillator circuit of a one of the pair of processing elements to provide the clock signal as the master clock signal to the clock generator of each of the pair of processing elements.
Claim 2
Dependent Claim
193 words
Apparatus for providing clock signals synchronized to a master clock signal for at least a pair of synchronous processing elements, comprising: each of the pair of processing elements including: a master oscillator circuit to produce a clock signal, a clock generator circuit coupled to receive the master clock signal to produce the synchronized clock signals therefrom for such one of the pair of processing elements, the clock generator circuit having a voltage controlled oscillator circuit responsive to a phase voltage to produce a first clock signal that is synchronous with the master clock signal, a counter circuit coupled to receive the first clock signal to produce a number of divisions of the first clock signal that includes the synchronized clock signals and a replica of the master clock signal, and a phase compare means coupled to receive the master clock signal and the replica of the master clock signal to produce the phase voltage; and means for coupling the master oscillator circuit of a one of the pair of processing elements to provide the clock signal as the master clock signal to the clock generator of each of the pair of processing elements.
Claim 3
Dependent Claim
22 words
The apparatus of claim 1, wherein the master oscillator circuit of each of the pair of processing elements includes a crystal oscillator.
Claim 4
Dependent Claim
44 words
The apparatus of claim 2, wherein the crystal oscillator produces a base clock signal with a frequency of F, and wherein the master oscillator includes a divide-by-N counter that receives the base clock signal to produce the clock signal with a frequency of F/N.
Claim 5
Dependent Claim
45 words
The apparatus of claim 1, wherein the phase compare means of each clock generator circuit operates to produce a LOCK signal when the master clock signal and the replica of the master clock signal are out of phase from one another by a predetermined amount.
Claim 6
Dependent Claim
71 words
The apparatus of claim 4, each processing element including a compare circuit coupled to receive the LOCK signals produced by the clock generator circuits to produce an output signal indicating that at least the clock generator circuit of a one of the pair of processing elements is producing synchronized clock signals out of phase with those produced by the clock generator circuit of the other of the pair of processing elements.
Claim 7
Independent Claim
194 words
A method for providing clock signals synchronized to a master clock signal for each of at least a pair of processing elements, including the steps of: providing at least one of the pair of processing elements with a master oscillator circuit to produce the master clock signal; providing each of the pair of processing elements with a clock generator circuit coupled to receive the master clock signal to produce therefrom the synchronized clock signals for such processing element, the clock generator circuit including: an oscillator circuit responsive to a phase voltage to produce a first clock signal that is synchronous with the master clock signal, a counter circuit coupled to receive the first clock signal produce a number of divisions of the first clock signal forming the synchronized clock signals and a replica of the master clock signal, and a phase compare means coupled to receive the master clock signal and the replica of the master clock signal to produce the phase voltage; and coupling the master oscillator circuit of a one of the pair of processing elements to provide the master clock signal for the clock generator o the pair of processing elements.
Claim 8
Independent Claim
194 words
A method for providing clock signals synchronized to a master clock signal for each of at least a pair of processing elements, including the steps of: providing at least one of the pair of processing elements with a master oscillator circuit to produce the master clock signal; providing each of the pair of processing elements with a clock generator circuit coupled to receive the master clock signal to produce therefrom the synchronized clock signals for such processing element, the clock generator circuit including: an oscillator circuit responsive to a phase voltage to produce a first clock signal that is synchronous with the master clock signal, a counter circuit coupled to receive the first clock signal produce a number of divisions of the first clock signal forming the synchronized clock signals and a replica of the master clock signal, and a phase compare means coupled to receive the master clock signal and the replica of the master clock signal to produce the phase voltage; and coupling the master oscillator circuit of a one of the pair of processing elements to provide the master clock signal for the clock generator o the pair of processing elements.
Claim 9
Independent Claim
195 words
A method for providing clock signals synchronized to a master clock signal for each of at least a pair of synchronous processing elements, including the steps of: providing each of the pair of processing elements with a clock generator circuit coupled to receive the master clock signal to produce therefrom the synchronized clock signals, the clock generator circuit including: an oscillator circuit responsive to a phase voltage to produce a first clock signal that is synchronous with the master clock signal, a counter circuit coupled to receive the first clock signal produce a number of divisions of the first clock signal forming the synchronized clock signals and a replica of the master clock signal, and a phase compare means coupled to receive the master clock signal and the replica of the master clock signal to produce the phase voltage; providing each of the pair of processing elements with a master oscillator circuit to produce a clock signal; and coupling the master oscillator circuit of a one of the pair of processing elements to provide the clock signal as the master clock signal to the clock generator circuits for each of the pair of processing elements.
Claim 10
Independent Claim
195 words
A method for providing clock signals synchronized to a master clock signal for each of at least a pair of synchronous processing elements, including the steps of: providing each of the pair of processing elements with a clock generator circuit coupled to receive the master clock signal to produce therefrom the synchronized clock signals, the clock generator circuit including: an oscillator circuit responsive to a phase voltage to produce a first clock signal that is synchronous with the master clock signal, a counter circuit coupled to receive the first clock signal produce a number of divisions of the first clock signal forming the synchronized clock signals and a replica of the master clock signal, and a phase compare means coupled to receive the master clock signal and the replica of the master clock signal to produce the phase voltage; providing each of the pair of processing elements with a master oscillator circuit to produce a clock signal; and coupling the master oscillator circuit of a one of the pair of processing elements to provide the clock signal as the master clock signal to the clock generator circuits for each of the pair of processing elements.
Claim 11
Dependent Claim
199 words
A processing system having at least a pair of processor units formed to be physically separate from one another, each of the processor units having a clock generator circuit operating to produce a plurality of clock signals synchronized to a master clock signal provided by a master clock generator, a method of providing the master clock signal to the clock generator circuit of each of the pair of processor units, including the steps of: providing at least one of the processor units with the master clock generator; coupling the master clock signal from the master clock generator to the clock generator circuit of other of the processor units that includes a first signal line; and coupling the master clock signal from the master clock generator to the clock generator of the one of the pair of processor units by a second signal line that includes an intermediate signal line that leaves the one processing unit and returns to the one processing unit to apply the master clock signal to the clock generator of the one processor unit for introducing a first delay that approximates a second delay imposed on the master clock signal coupled to the other processor unit.
Claim 12
Dependent Claim
199 words
A processing system having at least a pair of processor units formed to be physically separate from one another, each of the processor units having a clock generator circuit operating to produce a plurality of clock signals synchronized to a master clock signal provided by a master clock generator, a method of providing the master clock signal to the clock generator circuit of each of the pair of processor units, including the steps of: providing at least one of the processor units with the master clock generator; coupling the master clock signal from the master clock generator to the clock generator circuit of other of the processor units that includes a first signal line; and coupling the master clock signal from the master clock generator to the clock generator of the one of the pair of processor units by a second signal line that includes an intermediate signal line that leaves the one processing unit and returns to the one processing unit to apply the master clock signal to the clock generator of the one processor unit for introducing a first delay that approximates a second delay imposed on the master clock signal coupled to the other processor unit.
Claim 13
Dependent Claim
22 words
The processing system of claim 8, including the step of forming each of the pair of processing units on separate circuit boards.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-17 | 2001-05-19 | 2001-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-17 | 2005-05-19 | 2005-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-17 | 2009-05-19 | 2009-11-18 | $7700.00 | Window Closed / Lapsed |