PN code synchronizing method and transmitter and receiver in spread spectrum communication systems

Claim 2

A PN code synchronizing method in spread spectrum communication systems using a plurality of traffic channels and at least one synchronous channel, comprising a step of calculating a value by multiplying an internal status of a PN code generating shift register at a time t by M-th power of a matrix H (H M ) that is preset in advance and transmitting said value to a receiver through said synchronous channel.

Claim 3

The PN code synchronizing method in spread spectrum communication systems of claim 1, wherein said matrix H is derived from a PN code generating polynomial.

Claim 4

The PN code synchronizing method in spread spectrum communication systems of claim 1, comprising: (1) step of calculating said matrix H based on tap locations of said PN code generating shift register; and (2) step of calculating an internal status of said PN code generating shift register at a time t+M by multiplying said internal status of said PN code generating shift register at the time t by M-th power of said matrix H, and transmitting said internal status of said PN code generating shift register at the time t+M through said synchronous channel.

Claim 5

The PN code synchronizing method in spread spectrum communication systems of claim 3, wherein said (2) step comprising: (a) step of clearing as 0 all the contents of an n bit×1 word memory for storing said internal status of said PN code generating shift register at the time t+M, where length of said PN code generating shift register is n; (b) step of storing said internal status of said PN code generating shift register at the time t into a 1 bit×n word memory; (c) step of storing the contents of said matrix H M into an n bit×n word memory; (d) step of detecting an address storing 1 in said 1 bit×n word memory from the first address one by one, when having detected an address storing t calculating an exclusive-OR of the contents of an address of said n bit×n word memory which is corresponding to a detected address storing 1 of said 1 bit×n word memory and the contents of said n bit×1 word memory, and storing a calculation result into said n bit×1 word memory; and (e) step of repeating said (d) step n times and storing said internal status of said PN code generating shift register at the time t+M into said n bit×1 word memory.

Claim 6

The PN code synchronizing method in spread spectrum communication systems of claim 2, further comprising, in a reception side; (3) step of receiving said internal status of said PN code generating shift register at the time t+M transmitted through said synchronous channel, setting said internal status of said PN code generating shift register at the time t+M in a shift register of said receiver.

Claim 7

A PN code synchronizing method in spread spectrum communication systems using a plurality of traffic channels and at least one synchronous channel, comprising: (1) step of calculating a matrix H based on tap locations of a PN code generating shift register; (2) step of calculating an internal status of said PN code generating shift register at a time t+M by multiplying an internal status of a PN code generating shift register at a time t by M-th power of said matrix H (H M ), and transmitting said internal status of said PN code generating shift register at the time t+M through said synchronous channel; and (3) step of receiving said internal status of said PN code generating shift register at the time t+M transmitted through said synchronous channel, setting said internal status of said PN code generating shift register at the time t+M in a shift register of said receiver.

Claim 8

A PN code synchronizing method in spread spectrum communication systems using a plurality of traffic channels and at least one synchronous channel, comprising: (1) step of calculating a matrix H based on tap locations of a PN code generating shift register; (2) step of calculating an internal status of said PN code generating shift register at a time t+M by multiplying an internal status of a PN code generating shift register at a time t by M-th power of said matrix H (H M ), and transmitting said internal status of said PN code generating shift register at the time t+M through said synchronous channel; and (3) step of receiving said internal status of said PN code generating shift register at the time t+M transmitted through said synchronous channel, setting said internal status of said PN code generating shift register at the time t+M in a shift register of said receiver.

Claim 9

The PN code synchronizing method in spread spectrum communication systems of claim 6, wherein said (2) step comprising: (a) step of clearing as 0 all the contents of an n bit×1 word memory for storing said internal status of said PN code generating shift register at the time t+M, where length of said PN code generating shift register is n; (b) step of storing said internal status of said PN code generating shift register at the time t into a 1 bit×n word memory; (c) step of storing the contents of said matrix H M into an n bit×n word memory; (d) step of detecting an address storing 1 in said 1 bit×n word memory from the first address one by one, when having detected an address storing 1 calculating an exclusive-OR of the contents of an address of said n bit×n word memory which is corresponding to a detected address storing 1 of said 1 bit×n word memory and the contents of said n bit×1 word memory, and storing a calculation result into said n bit×1 word memory; (e) step of repeating said (d) step n times and storing said internal status of said PN code generating shift register at the time t+M into said n bit×1 word memory; and (f) step of transmitting the contents stored in said n bit×1 word memory through said synchronous channel.

Claim 10

A spread spectrum transmitter comprising: a shift register for generating a PN code; and a calculating means for calculating an internal digital value of the shift register after the elapse of time "M" using a matrix H M , wherein the term "M" represents the time from when a receiver receives a synchronization channel to when the receiver receives a signal on the communication channel.

Claim 11

A spread spectrum transmitter comprising: a shift register for generating a PN code; and a calculating means for calculating an internal digital value of the shift register after the elapse of time "M" using a matrix H M , wherein the term "M" represents the time from when a receiver receives a synchronization channel to when the receiver receives a signal on the communication channel.

Claim 12

A spread spectrum transmitter comprising: a shift register for generating a PN code; a calculating means for calculating an internal status of shift register at a time after a predetermined time interval M from a time t, said calculating means comprising: a first storing means for storing said internal status of shift register at the time t; a second storing means for storing M-th power of a matrix H (H M ) derived from tap locations of said shift register; a multiplying means for multiplying the contents stored in said first storing means and the contents of said second storing means; and a third storing means for storing a calculation result of said multiplying means.

Claim 13

A spread spectrum transmitter comprising: a shift register for generating a PN code; a calculating means for calculating an internal status of shift register at a time after a predetermined time interval M from a time t, said calculating means comprising: a first storing means for storing said internal status of shift register at the time t; a second storing means for storing M-th power of a matrix H (H M ) derived from tap locations of said shift register; a multiplying means for multiplying the contents stored in said first storing means and the contents of said second storing means; and a third storing means for storing a calculation result of said multiplying means.

Claim 14

The spread spectrum transmitter of claim 9, wherein said calculating means comprising: a 1 bit×n word memory for storing said internal status of shift register at the time t, where length of said shift register is n; an n bit×n word memory for storing a matrix H M derived from tap locations of said shift register; an n bit×1 word memory for storing an internal status of shift register at a time t+M; and a calculating section for clearing as 0 all the contents of said n bit×1 word memory and calculating an exclusive-OR of the contents of an address of said n bit×n word memory which is corresponding to an address of said 1 bit×n word memory and the contents of said n bit×1 word memory.

Claim 15

The spread spectrum transmitter of claim 10, wherein said calculating section comprising: a deciding circuit for fetching the contents of said 1 bit×n word memory from address 1 to address n one by one, and detecting an address storing 1; a calculating circuit for calculating, when having detected an address storing 1, exclusive-OR of the contents of an address of said n bit×n word memory which is corresponding to the detected address storing 1 of said 1 bit×n word memory and the contents of said n bit×1 word memory and storing this calculation result into said n bit×1 word memory; a counter for counting a number of operations of said deciding circuit.

Claim 16

A spread spectrum transmitter comprising: a shift register for generating a PN code; a calculating means for calculating an internal status of shift register at a time after a predetermined time interval M from a time t; and further comprising a transmitting means for transmitting an internal status of shift register at a time after the time interval M from the time t.

Claim 17

A spread spectrum transmitter comprising: a shift register for generating a PN code; a calculating means for calculating an internal status of shift register at a time after a predetermined time interval M from a time t; and further comprising a transmitting means for transmitting an internal status of shift register at a time after the time interval M from the time t.

Claim 18

A spread spectrum transmitter comprising: a shift register for generating a PN code; a 1 bit×n word memory for storing an internal status of shift register at a time t, where length of said shift register is n; an n bit×n word memory for storing M-th power of a matrix H (H M ) derived from tap locations of said shift register; an n bit×1 word memory for storing an internal status of shift register at a time t+M; a deciding means for fetching the contents of said 1 bit×n word memory from address 1 to address n one by one, and detecting an address storing 1; a counter for counting a number of operations of said deciding means; and an exclusive-OR calculating means for calculating, when having detected an address storing 1, exclusive-OR of the contents of an address of said n bit×n word memory which is corresponding to the detected address storing 1 of said 1 bit×n word memory and the contents of said n bit×1 word memory and storing this calculation result into said n bit×1 word memory until the counted number of said counter becomes n.

Claim 19

A spread spectrum transmitter comprising: a shift register for generating a PN code; a 1 bit×n word memory for storing an internal status of shift register at a time t, where length of said shift register is n; an n bit×n word memory for storing M-th power of a matrix H (H M ) derived from tap locations of said shift register; an n bit×1 word memory for storing an internal status of shift register at a time t+M; a deciding means for fetching the contents of said 1 bit×n word memory from address 1 to address n one by one, and detecting an address storing 1; a counter for counting a number of operations of said deciding means; and an exclusive-OR calculating means for calculating, when having detected an address storing 1, exclusive-OR of the contents of an address of said n bit×n word memory which is corresponding to the detected address storing 1 of said 1 bit×n word memory and the contents of said n bit×1 word memory and storing this calculation result into said n bit×1 word memory until the counted number of said counter becomes n.

Claim 20

The spread spectrum transmitter of claim 13, further comprising transmitting means for transmitting the contents of said n bit×1 word memory.

Claim 21

A spread spectrum receiver comprising: a shift register being set in an internal status of shift register at the time s that has been transmitted, for generating a PN code; and a calculating means for calculating an internal status of shift register at a time s+N based on said internal status of shift register at the time s.

Claim 22

A spread spectrum receiver comprising: a shift register being set in an internal status of shift register at the time s that has been transmitted, for generating a PN code; and a calculating means for calculating an internal status of shift register at a time s+N based on said internal status of shift register at the time s.

Claim 23

The spread spectrum receiver of claim 15, wherein said calculating means comprising: a first storing means for storing an internal status of shift register at the time s; a second storing means for storing N-th power of a matrix H (H N ) derived from tap locations of said shift register; a multiplying means for multiplying the contents stored in said first storing means and the contents of said second storing means; and a third storing means for storing a calculation result of said multiplying means.

Claim 24

The spread spectrum receiver of claim 15, wherein said calculating means comprising: a 1 bit×n word memory for storing said internal status of shift register at the time s, where length of said shift register is n; an n bit×n word memory for storing a matrix H N derived from tap locations of said shift register; an n bit×1 word memory for storing an internal status of shift register at a time s+N; and a calculating section for clearing as 0 all the contents of said n bit×1 word memory and calculating an exclusive-OR of the contents of an address of said n bit×n word memory which is corresponding to an address of said 1 bit×n word memory and the contents of said n bit×1 word memory.

Claim 25

The spread spectrum receiver of claim 17, wherein said calculating section comprising: a deciding circuit for fetching the contents of said 1 bit×n word memory from address 1 to address n one by one, and detecting an address storing 1; a calculating means for calculating, when having detected an address storing 1, exclusive-OR of the contents of an address of said n bit×n word memory which is corresponding to the detected address storing 1 of said 1 bit×n word memory and the contents of said n bit×1 word memory and storing this calculation result into said n bit×1 word memory; and a counter for counting a number of operations of said deciding circuit.

Claim 26

A spread spectrum receiver comprising: a shift register being set in an internal status of shift register at the time s that has been transmitted, for generating a PN code; a 1 bit×n word memory for storing an internal status of shift register at a time s, where length of said shift register is n; an n bit×n word memory for storing N-th power of a matrix H derived from tap locations of said shift register; an n bit×1 word memory for storing an internal status of shift register at a time s+N; a deciding means for fetching the contents of said 1 bit×n word memory from address 1 to address n one by one, and detecting an address storing 1; a counter for counting a number of operations of said deciding means; and an exclusive-OR calculating means for calculating, when having detected an address storing 1, exclusive-OR of the contents of an address of said n bit×n word memory which is corresponding to the detected address storing 1 of said 1 bit×n word memory and the contents of said n bit×1 word memory and storing this calculation result into said n bit×1 word memory until the counted number by said counter becomes n.

Claim 27

A spread spectrum receiver comprising: a shift register being set in an internal status of shift register at the time s that has been transmitted, for generating a PN code; a 1 bit×n word memory for storing an internal status of shift register at a time s, where length of said shift register is n; an n bit×n word memory for storing N-th power of a matrix H derived from tap locations of said shift register; an n bit×1 word memory for storing an internal status of shift register at a time s+N; a deciding means for fetching the contents of said 1 bit×n word memory from address 1 to address n one by one, and detecting an address storing 1; a counter for counting a number of operations of said deciding means; and an exclusive-OR calculating means for calculating, when having detected an address storing 1, exclusive-OR of the contents of an address of said n bit×n word memory which is corresponding to the detected address storing 1 of said 1 bit×n word memory and the contents of said n bit×1 word memory and storing this calculation result into said n bit×1 word memory until the counted number by said counter becomes n.