US5689507A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal processing system
Assignee: US Philips Corp
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Filing: 1995-06-30
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Granted: 1997-11-18
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Expires: 2015-06-30
Abstract
Abstract A signal processing system comprising a source apparatus coupled to a destination apparatus, the source apparatus being arranged for supplying the destination apparatus with a signal comprising video data, a time-stamp and synchronization data representing a time-value of an instant of said supplying, the destination apparatus being arranged for receiving the signal, synchronizing a time-value of a clock in accordance with the synchronization data, detecting when the time-value of the clock corresponds to the time-stamp and for thereupon presenting the video data at an output. The system includes a bus operable according to a time-slot allocation protocol, the source apparatus supplying the signal to the destination apparatus via the bus, the source apparatus including a first interface unit for buffering the signal until an allocated time-slot is available on the bus, the source apparatus setting the synchronization data according to an instant the signal is supplied to the first interface unit. The destination apparatus including a buffer, for buffering the signal prior to synchronizing the time-value of the clock for a predetermined interval, at least equal to a maximum wait-interval for the allocation of a time-slot on the bus, has elapsed after the instant the signal is supplied to the first interface unit.
Inventors
- 👤 Rudolf H.J. Bloks
- 👤 Marnix C. Vlot
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:25
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/24; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/40052; H04L12/40058; H04J3/247; H04L12/40117; H04L12/407; H04L12/417; H04L12/64; H04L12/6418; H04N; H04N19/00; H04N19/42; H04N19/60; H04N19/61; H04N21/00; H04N21/40; H04N21/41; H04N21/4104; H04N21/4135; H04N21/43; H04N21/4302; H04N21/4305; H04N21/4307; H04N21/43072; H04N21/434; H04N21/4342; H04N21/436; H04N21/4363; H04N21/43632; H04L2012/6432; H04L2012/6435; H04L2012/6445; H04L2012/6456; H04L2012/6483; H04L2012/6489
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
233 words
A signal processing system comprising a source apparatus coupled to a destination apparatus, the source apparatus being arranged for supplying a signal to the destination apparatus, the signal comprising video data and a time-stamp, the destination apparatus comprising a clock and means for detecting when a time-value of the clock corresponds to the time-stamp and for thereupon presenting the video data at an output, the signal further comprising synchronization data representing a time-value associated with an instant of delivery of the signal in the destination apparatus, the destination apparatus being arranged for adjusting the time-value of the clock according to the synchronization data, the system being characterized in that said system comprises a bus operable according to a time-slot allocation protocol, the source apparatus comprising a first interface unit for buffering the signal until an allocated time-slot is available on the bus, the synchronization data being set according to an instant of delivery of the signal to the first interface unit, the source apparatus supplying the signal to the destination apparatus via the bus, the destination apparatus comprising a buffer for buffering the signal prior to adjusting the time-value of the clock, the buffering in the buffer lasting until a predetermined interval, at least equal to a maximum wait-interval for the allocation of a time-slot on the bus, has elapsed after the instant of delivery of the signal to the first interface unit.
Claim 2
Dependent Claim
233 words
A signal processing system comprising a source apparatus coupled to a destination apparatus, the source apparatus being arranged for supplying a signal to the destination apparatus, the signal comprising video data and a time-stamp, the destination apparatus comprising a clock and means for detecting when a time-value of the clock corresponds to the time-stamp and for thereupon presenting the video data at an output, the signal further comprising synchronization data representing a time-value associated with an instant of delivery of the signal in the destination apparatus, the destination apparatus being arranged for adjusting the time-value of the clock according to the synchronization data, the system being characterized in that said system comprises a bus operable according to a time-slot allocation protocol, the source apparatus comprising a first interface unit for buffering the signal until an allocated time-slot is available on the bus, the synchronization data being set according to an instant of delivery of the signal to the first interface unit, the source apparatus supplying the signal to the destination apparatus via the bus, the destination apparatus comprising a buffer for buffering the signal prior to adjusting the time-value of the clock, the buffering in the buffer lasting until a predetermined interval, at least equal to a maximum wait-interval for the allocation of a time-slot on the bus, has elapsed after the instant of delivery of the signal to the first interface unit.
Claim 3
Dependent Claim
103 words
A signal processing system according to claim 1, wherein the source apparatus and the destination apparatus comprise a first further clock and a second further clock respectively, means for synchronizing the first and second further clock to each other by further signals via the bus, the source apparatus being arranged for obtaining a sample value from the first further clock at the instant of delivery to the first interface unit, and transmitting information about that sample value to the destination apparatus, the buffer buffering the signal until the second further clock exceeds the sample value by a predetermined offset representing the predetermined interval.
Claim 4
Dependent Claim
109 words
A signal processing system according to claim 2, wherein the signal comprises packets, mutually separated by pauses, the sample value being obtained upon delivery of a first part of a packet to the first interface unit, the source apparatus being arranged for obtaining a further sample value from the first further clock upon delivery of a second part of said packet to the first interface unit, the buffer regulating a speed at which the signal is output such that the number clock cycles between outputting the first and the second part of the packet is substantially equal to the difference between the sample value and the further sample value.
Claim 5
Dependent Claim
48 words
A signal processing system according to claim 3, wherein the first part precedes the second part in the packet, the first interface unit being arranged for transmitting information about at least a most significant part of the sample value as a difference relative to the further sample value.
Claim 6
Dependent Claim
25 words
A signal processing system according to claim 4, wherein the first interface unit is arranged for transmitting a least significant part of the sample value.
Claim 7
Dependent Claim
32 words
A signal processing system according to claim 5, wherein said least significant part of the sample value represents a phase in a period a pattern of periodically allocated time-slots on the bus.
Claim 8
Dependent Claim
66 words
A signal processing system according to claim 1, wherein the source apparatus is arranged for reproducing the signal from a record carrier, on which it is stored together with a further time-stamp for regenerating the timing of the signal for supplying it to the destination apparatus, the timing of the signal being regenerated according to the time-stamp prior to supplying it to the first interface unit.
Claim 9
Dependent Claim
21 words
A signal processing system according to claim 1, wherein the signal supplied to the destination apparatus is an MPEG based signal.
Claim 10
Dependent Claim
66 words
A signal processing system according to claim 3, wherein the source apparatus is arranged for reproducing the signal from a record carrier, on which it is stored together with a further time-stamp for regenerating the timing of the signal for supplying it to the destination apparatus, the timing of the signal being regenerated according to the time-stamp prior to supplying it to the first interface unit.
Claim 11
Dependent Claim
66 words
A signal processing system according to claim 6, wherein the source apparatus is arranged for reproducing the signal from a record carrier, on which it is stored together with a further time-stamp for regenerating the timing of the signal for supplying it to the destination apparatus, the timing of the signal being regenerated according to the time-stamp prior to supplying it to the first interface unit.
Claim 12
Dependent Claim
21 words
A signal processing system according to claim 3, wherein the signal supplied to the destination apparatus is an MPEG based signal.
Claim 13
Dependent Claim
21 words
A signal processing system according to claim 7, wherein the signal supplied to the destination apparatus is an MPEG based signal.
References Cited (Backward Citations)
US5166927A
Cited
US5485507A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-17 | 2001-05-19 | 2001-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-17 | 2005-05-19 | 2005-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-17 | 2009-05-19 | 2009-11-18 | $7700.00 | Window Closed / Lapsed |