Reservation station with a pseudo-FIFO circuit for scheduling dispatch of instructions

Claim 1

A reservation station (RS) that dispatches micro-operations (uops) specified by instruction of a microprocessor to an execution unit, the RS comprising: a memory array having a plurality of entries, a uop being stored at each entry with an age representing a temporal ordering of all uops stored therein; control circuitry associated with each entry of the memory array that resets the age of a new uop and increments ages of previously stored uops when the new uop is written into the array, the control circuitry also including comparison logic that compares a current age of each entry with an oldest age and produces a priority pointer identifies an oldest entry having the oldest age; an age detection circuit coupled with the control circuitry that detects the oldest age of the memory array, the age detection circuit broadcasting the oldest age through the memory array; scheduling logic that selects a ready entry from the plurality of entries of the memory array for dispatch to a port of the execution unit, a beginning scan point for selection of the ready entry being determined by the priority pointer.