A/D converter with charge-redistribution DAC and split summation of main and correcting DAC outputs

Claim 1

The method of converting an analog signal to a digital signal by a successive-approximation process carried out by an integrated-circuit (IC) chip aria including the following steps: supplying bits of a successive-approximation word to a first group of switched capacitors to produce corresponding analog signals; directing said analog signals to one input terminal of a comparator; utilizing stored calibration coefficients to develop control signals for a second group of switched capacitors developing analog correction signals for the respective individual bits of said successive-approximation word; computing said calibration coefficients at the time manufacture of said IC chip; said calibration coefficients being computed by circuitry located off of said IC chip and operable to activate a sequence of operations of digital switch control circuitry for said second group of switched capacitors; said sequence of operations producing calibration coefficients for each bit of said successive-approximation word; developing multi-bit correction signals responsive to each of said calibrate coefficients for each bit of said successive-approximation word which is turned on as a result of carrying out said successive-approximation process; summing said multi-bit correction signals to develop a composite correction signal for all of the turned-on bits; applying said composite correction signal to said other comparator input terminal; and directing the output of said comparator to logic means for controlling the successive-approximation processing to determine the bits of the final digital output signal.

Claim 2

The method of converting an analog signal to a digital signal by a successive-approximation process carried out by an integrated-circuit (IC) chip aria including the following steps: supplying bits of a successive-approximation word to a first group of switched capacitors to produce corresponding analog signals; directing said analog signals to one input terminal of a comparator; utilizing stored calibration coefficients to develop control signals for a second group of switched capacitors developing analog correction signals for the respective individual bits of said successive-approximation word; computing said calibration coefficients at the time manufacture of said IC chip; said calibration coefficients being computed by circuitry located off of said IC chip and operable to activate a sequence of operations of digital switch control circuitry for said second group of switched capacitors; said sequence of operations producing calibration coefficients for each bit of said successive-approximation word; developing multi-bit correction signals responsive to each of said calibrate coefficients for each bit of said successive-approximation word which is turned on as a result of carrying out said successive-approximation process; summing said multi-bit correction signals to develop a composite correction signal for all of the turned-on bits; applying said composite correction signal to said other comparator input terminal; and directing the output of said comparator to logic means for controlling the successive-approximation processing to determine the bits of the final digital output signal.