Data driver generating two sets of sampling signals for sequential-sampling mode and simultaneous-sampling mode

Claim 2

A data driver for sampling display data and supplying sampled display data to a display device, comprising: a shift register circuit for sequentially shifting a sampling start pulse in response to a clock signal to thereby produce a plurality of first sampling signals in sequence; a plurality of sample/hold circuits each responding to an associated one of second sampling signals to sample said display data and supply sampled display data to said display device; and a switching circuit coupled between said shift register circuit and said sample/hold circuits and supplied with a control signal, said switching circuit transferring, when said control signal is maintained at a first logic level, said first sampling signals to said sample/hold circuits as said second sampling signals, respectively, and transferring, when said control signal is maintained at a second logic level, selected ones of said first sampling signals such that each of said selected ones of said first sampling signals is transferred in common to associated two or more of said sample/hold circuits, as the second sampling signals thereof.

Claim 3

The data driver as claimed in claim 1, wherein said switching circuit includes a plurality of level shift circuits each converting a level of one of said first sampling signals supplied thereto and producing a corresponding one of said second sampling signals.

Claim 4

The data driver as claimed in claim 1, wherein said switching circuit includes a plurality of switch circuits each formed of a transfer gate.

Claim 5

A data driver for sampling display data and supplying sampled display data to a display device, comprising: a shift register circuit for sequentially shifting a sampling start pulse in response to a clock signal to thereby produce a plurality of first sampling signals in sequence; a plurality of sample/hold circuits each responding to an associated one of second sampling signals to sample said display data and supply sampled display data to said display device; and a switching circuit coupled between said shift register circuit and said sample/hold circuits and supplied with a control signal, said switching circuit transferring said first sampling signals to said sample/hold circuits as said second sampling signals, respectively, when said control signal takes a first logic level and transferring selected ones of said first sampling signals to said sample/hold circuits such that one of said selected ones of said first sampling signals is transferred in common to associated ones of said sample/hold circuits when said control signal takes a second logic level, wherein said switching circuit includes a plurality of analog switches each formed of a P-channel MOS transistor and an N-channel MOS transistor.

Claim 6

A data driver for sampling display data and supplying sampled display data to a display device, comprising: a shift register circuit for sequentially shifting a sampling start pulse in response to a clock signal to thereby produce a plurality of first sampling signals in sequence; a plurality of sample/hold circuits each responding to an associated one of second sampling signals to sample said display data and supply sampled display data to said display device; and a switching circuit coupled between said shift register circuit and said sample/hold circuits and supplied with a control signal, said switching circuit transferring said first sampling signals to said sample/hold circuits as said second sampling signals, respectively, when said control signal takes a first logic level and transferring selected ones of said first sampling signals to said sample/hold circuits such that one of said selected ones of said first sampling signals is transferred in common to associated ones of said sample/hold circuits when said control signal takes a second logic level, wherein said switching circuit includes a plurality of analog switches each formed of a P-channel MOS transistor and an N-channel MOS transistor.

Claim 7

A data driver comprising a plurality of sampling signal input terminals supplied respectively with a plurality of sampling signals, a plurality of sampling signal output terminals, a control terminal supplied with a control signal, a switching circuit coupled to said sampling signal input terminals, said sampling signal output terminals and said control terminal and including a plurality of switches arranged such that first ones of said switches are turned ON and second ones of said switches are turned OFF when said control signal takes a first logic level to cause said sampling signals to appear at said sampling signal output terminals, respectively, and that third ones of said switches are turned ON and fourth ones of said switches are turned OFF when said control signal takes a second logic level to cause at least one of said sampling signals to appear in common at two or more ones of said sampling signal output terminals; and a plurality of sample/hold circuits each coupled to an associated one of said sampling signal output terminals and sampling display data in response to a sampling signal appearing at said associated one of said sampling signal output terminals.

Claim 8

A data driver comprising a plurality of sampling signal input terminals supplied respectively with a plurality of sampling signals, a plurality of sampling signal output terminals, a control terminal supplied with a control signal, a switching circuit coupled to said sampling signal input terminals, said sampling signal output terminals and said control terminal and including a plurality of switches arranged such that first ones of said switches are turned ON and second ones of said switches are turned OFF when said control signal takes a first logic level to cause said sampling signals to appear at said sampling signal output terminals, respectively, and that third ones of said switches are turned ON and fourth ones of said switches are turned OFF when said control signal takes a second logic level to cause at least one of said sampling signals to appear in common at two or more ones of said sampling signal output terminals; and a plurality of sample/hold circuits each coupled to an associated one of said sampling signal output terminals and sampling display data in response to a sampling signal appearing at said associated one of said sampling signal output terminals.

Claim 9

The data driver as claimed in claim 5, wherein said switches includes a plurality of first switches each connected between a selected one of said sampling signal input terminals and an associated one of said sampling signal output terminals and a plurality of second switches each connected between adjacent ones of said sampling signal output terminals.