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US5680554A
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Method and apparatus for arbitrating among processors for access to a common bus
Assignee: Transpacific Avartar LLC
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Filing: 1995-10-04
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Granted: 1997-10-21
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Expires: 2015-10-04
Abstract
Abstract A method and apparatus for arbitrating among a plurality of processors for access to a common system bus in a multi-processing system are provided. The bus arbitrating method includes the steps of detecting a request signal from a processor requesting access to the system bus, checking the number of other processors in the system requesting access to the system bus, providing access to the system bus by considering a priority factor among competing processors when the number of processors requesting access to the system bus is below a predetermined number, and providing access to the system bus by considering only a fairness factor when the number of processors requesting access to the system bus is not below the predetermined number. Accordingly, bus access speed can be improved by considering principles of both fairness and priority.
Inventors
- 👤 Seung-Gon Baek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:28
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
128 words
A bus arbitration method, comprising the steps of: detecting a request signal indicating that a first processor out of a plurality of processors in a system requests access to a system bus common to said plurality of processors; calculating a number representative of how many of said plurality of processors, other than said first processor, are requesting access to said system bus; determining whether said number is below a predetermined number; when said number is below said predetermined number, comparing priorities of said first processor and said plurality of processors, other than said first processor, that are requesting access to said system bus; and providing access to said system bus for one of said plurality of processors requesting access to said system bus and having a highest priority.
Claim 2
Dependent Claim
128 words
A bus arbitration method, comprising the steps of: detecting a request signal indicating that a first processor out of a plurality of processors in a system requests access to a system bus common to said plurality of processors; calculating a number representative of how many of said plurality of processors, other than said first processor, are requesting access to said system bus; determining whether said number is below a predetermined number; when said number is below said predetermined number, comparing priorities of said first processor and said plurality of processors, other than said first processor, that are requesting access to said system bus; and providing access to said system bus for one of said plurality of processors requesting access to said system bus and having a highest priority.
Claim 3
Dependent Claim
51 words
The bus arbitration method as claimed in claim 1, further comprising a step of generating a waiting signal for delaying arbitration of another one of said plurality of processors requesting access to said system bus while said one of said plurality of processors having said highest priority accesses said system bus.
Claim 4
Dependent Claim
60 words
The method of claim 1, further comprised of: said one of said plurality of processors having access to use said system bus temporarily delaying arbitration of another request for access to said system bus by another one of said plurality of processors requesting access to said system bus while said one of said plurality of processors accesses said system bus.
Claim 5
Dependent Claim
173 words
A bus arbitration method, comprising the steps of: detecting a request signal indicating that a first processor out of a plurality of processors in a system requests access to a system bus common to said plurality of processors; calculating a number representative of how many of said plurality of processors, other than said first processor, are requesting access to said system bus; when said number is below a predetermined number, determining whether a waiting signal has been generated by one of said plurality of processors requesting access to said system bus; when said waiting signal has been generated, providing access to said system bus for said one of said plurality of processors that generated said waiting signal; and when said number is not below said predetermined number, providing access to said system bus for one of said plurality of processors requesting access to said system bus and having a highest ranking according to a round-robin schedule that sequentially assigns said highest ranking to each one of said plurality of processors in said system.
Claim 6
Dependent Claim
173 words
A bus arbitration method, comprising the steps of: detecting a request signal indicating that a first processor out of a plurality of processors in a system requests access to a system bus common to said plurality of processors; calculating a number representative of how many of said plurality of processors, other than said first processor, are requesting access to said system bus; when said number is below a predetermined number, determining whether a waiting signal has been generated by one of said plurality of processors requesting access to said system bus; when said waiting signal has been generated, providing access to said system bus for said one of said plurality of processors that generated said waiting signal; and when said number is not below said predetermined number, providing access to said system bus for one of said plurality of processors requesting access to said system bus and having a highest ranking according to a round-robin schedule that sequentially assigns said highest ranking to each one of said plurality of processors in said system.
Claim 7
Dependent Claim
80 words
The method of claim 4, further comprised of: storing representations of each of said requests by said plurality of processors in the system, before calculating said number; and said one of said plurality of processors having access to use said system bus temporarily delaying arbitration of another request for access to said system bus by another one of said plurality of processors requesting access to said system bus while said one of said plurality of processors accesses said system bus.
Claim 8
Independent Claim
179 words
A device for arbitrating among a plurality of processors in a system having a system bus common to said plurality of processors, said device comprising: request signal processing means for determining a number representative of haw many of said plurality of processors are requesting access to said system bus, and for generating a control signal when said representative number is below a predetermined number; and priority comparing means for detecting, in response to said control signal, a waiting signal generated by one of said plurality of processors requesting access to said system bus, said priority comparing means allowing access to said system bus for said one of said plurality of processors that generated said waiting signal when said waiting signal is detected, and when said control signal is not detected, said priority comparing means allowing access to said system bus for one of said plurality of processors requesting access to said system bus having a highest ranking according to a round-robin schedule that sequentially assigns said highest ranking to each one of said plurality of processors in said system.
Claim 9
Independent Claim
179 words
A device for arbitrating among a plurality of processors in a system having a system bus common to said plurality of processors, said device comprising: request signal processing means for determining a number representative of haw many of said plurality of processors are requesting access to said system bus, and for generating a control signal when said representative number is below a predetermined number; and priority comparing means for detecting, in response to said control signal, a waiting signal generated by one of said plurality of processors requesting access to said system bus, said priority comparing means allowing access to said system bus for said one of said plurality of processors that generated said waiting signal when said waiting signal is detected, and when said control signal is not detected, said priority comparing means allowing access to said system bus for one of said plurality of processors requesting access to said system bus having a highest ranking according to a round-robin schedule that sequentially assigns said highest ranking to each one of said plurality of processors in said system.
Claim 10
Dependent Claim
88 words
The device as claimed in claim 6, wherein said request signal processing means comprises: a request signal detector for detecting a request signal indicative of a request by a corresponding one of said plurality of processors to access said system bus; and a request signal generator for determining, in response to detection of said request signal, said number representative of how many of said plurality of processors are requesting access to said system bus, and for generating said control signal when said number is below said predetermined number.
Claim 11
Dependent Claim
37 words
The device as claimed in claim 7, wherein said request signal processing means further comprises a request signal generation controller for controlling operation of said request signal generator in response to the detection of said request signal.
Claim 12
Dependent Claim
63 words
The device claimed in claim 7, comprised of said corresponding one of said plurality of processors having current access to use said system bus temporarily delaying arbitration of another request for access to said system bus by another one of said plurality of processors requesting access to said system bus while said corresponding one of said plurality of processors accesses said system bus.
Claim 13
Dependent Claim
44 words
The device as claimed in claim 7, further comprising signal transmission means for transmitting data from said corresponding one of said plurality of processors to said system bus when said corresponding one of said plurality of processors is provided access to said system bus.
Claim 14
Dependent Claim
107 words
The device as claimed in claim 10, wherein said signal transmission means comprises: first means for transmitting a first signal identifying said corresponding one of said plurality of processors; second means for transmitting a second signal representative of one of a read operation and a write operation to be performed by said corresponding one of said plurality of processors; third means for transmitting a third signal representative of an address within said system where said read operation or said write operation will be performed; and fourth means for transmitting a fourth signal representative of a number of bits involved in said read operation or said write operation.
Claim 15
Dependent Claim
181 words
A bus arbitration method, comprising the steps of: detecting a request signal indicating that a first processor out of a plurality of processors in a system requests access to a system bus common to said plurality of processors; computing a number representative of how many of said plurality of processors, other than said first processor, are requesting access to said system bus; when said number is below a predetermined number, determining whether one of said plurality of processors requesting access to said system bus has a priority in accessing said system bus; when one of said plurality of processors requesting access to said system bus has said priority, providing access to said system bus for said one of said plurality of processors having said priority; and when said number is not below said predetermined number, providing access to said system bus for one of said plurality of processors requesting access to said system bus and having a highest ranking according to a round-robin schedule that sequentially assigns said highest ranking to each one of said plurality of processors in said system.
Claim 16
Dependent Claim
181 words
A bus arbitration method, comprising the steps of: detecting a request signal indicating that a first processor out of a plurality of processors in a system requests access to a system bus common to said plurality of processors; computing a number representative of how many of said plurality of processors, other than said first processor, are requesting access to said system bus; when said number is below a predetermined number, determining whether one of said plurality of processors requesting access to said system bus has a priority in accessing said system bus; when one of said plurality of processors requesting access to said system bus has said priority, providing access to said system bus for said one of said plurality of processors having said priority; and when said number is not below said predetermined number, providing access to said system bus for one of said plurality of processors requesting access to said system bus and having a highest ranking according to a round-robin schedule that sequentially assigns said highest ranking to each one of said plurality of processors in said system.
Claim 17
Dependent Claim
50 words
The bus arbitration method as claimed in claim 10, further comprising a step of generating a waiting signal for delaying arbitration of another one of said plurality of processors requesting access to said system bus while said one of said plurality of processors having said priority accesses said system bus.
Claim 18
Dependent Claim
80 words
The method of claim 12, further comprised of: storing representations of each of said requests by said plurality of processors in the system, before computing said number; and said one of said plurality of processors having access to use said system bus temporarily delaying arbitration of another request for access to said system bus by another one of said plurality of processors requesting access to said system bus while said one of said plurality of processors accesses said system bus.
Claim 19
Independent Claim
163 words
A device for arbitrating among a plurality of processors in a system having a system bus common to said plurality of processors, said device comprising: request signal processing means for determining a number representative of how many of said plurality of processors are requesting access to said system bus, and for generating a control signal when said number is below a predetermined number; and priority comparing means for comparing priorities among said plurality of processors requesting access to said system bus and allowing access to said system bus for one of said plurality of processors that has a highest priority when said control signal is generated, and when said control signal is not generated, said priority comparing means allowing access to said system bus for one of said plurality of processors requesting access to said system bus having a highest ranking according to a round-robin schedule that sequentially assigns said highest ranking to each one of said plurality of processors in said system.
Claim 20
Independent Claim
163 words
A device for arbitrating among a plurality of processors in a system having a system bus common to said plurality of processors, said device comprising: request signal processing means for determining a number representative of how many of said plurality of processors are requesting access to said system bus, and for generating a control signal when said number is below a predetermined number; and priority comparing means for comparing priorities among said plurality of processors requesting access to said system bus and allowing access to said system bus for one of said plurality of processors that has a highest priority when said control signal is generated, and when said control signal is not generated, said priority comparing means allowing access to said system bus for one of said plurality of processors requesting access to said system bus having a highest ranking according to a round-robin schedule that sequentially assigns said highest ranking to each one of said plurality of processors in said system.
Claim 21
Dependent Claim
88 words
The device as claimed in claim 15, wherein said request signal processing means comprises: a request signal detector for detecting a request signal indicative of a request by a corresponding one of said plurality of processors to access said system bus; and a request signal generator for determining, in response to detection of said request signal, said number representative of how many of said plurality of processors are requesting access to said system bus, and for generating said control signal when said number is below said predetermined number.
Claim 22
Dependent Claim
37 words
The device as claimed in claim 16, wherein said request signal processing means further comprises a request signal generation controller for controlling operation of said request signal generator in response to the detection of said request signal.
Claim 23
Dependent Claim
46 words
The device as claimed in claim 16, wherein said request signal generator generates a waiting signal for delaying arbitration of another one of said plurality of processors requesting access to said system bus while said corresponding one of said plurality of processors accesses said system bus.
Claim 24
Dependent Claim
44 words
The device as claimed in claim 16, further comprising signal transmission means for transmitting data from said corresponding one of said plurality of processors to said system bus when said corresponding one of said plurality of processors is provided access to said system bus.
Claim 25
Dependent Claim
107 words
The device as claimed in claim 19, wherein said signal transmission means comprises: first means for transmitting a first signal identifying said corresponding one of said plurality of processors; second means for transmitting a second signal representative of one of a read operation and a write operation to be performed by said corresponding one of said plurality of processors; third means for transmitting a third signal representative of an address within said system where said read operation or said write operation will be performed; and fourth means for transmitting a fourth signal representative of a number of bits involved in said read operation or said write operation.
Claim 26
Dependent Claim
79 words
The device as claimed in claim 15, wherein when said control signal has been generated and none of said plurality of processors requesting access to said system bus has said highest priority, access to said system bus is provided to said one of said plurality of processors requesting access to said system bus having said highest ranking according to said round-robin schedule that sequentially assigns said highest ranking to each one of said plurality of processors in said system.
Claim 27
Dependent Claim
126 words
A bus arbitration method, comprising the steps of: detecting a request signal indicating that a first processor out of a plurality of processors in a system requests access to a system bus common to said plurality of processors; determining whether a number of said plurality of processors, other than said first processor, requesting access to said system bus is less than or equal to a predetermined number; when said number is less than or equal to said predetermined number, comparing priorities of said first processor and said plurality of processors, other than said first processor, requesting access to said system bus; and providing access to said system bus for one of said plurality of processors requesting access to said system bus and having a highest priority.
Claim 28
Dependent Claim
126 words
A bus arbitration method, comprising the steps of: detecting a request signal indicating that a first processor out of a plurality of processors in a system requests access to a system bus common to said plurality of processors; determining whether a number of said plurality of processors, other than said first processor, requesting access to said system bus is less than or equal to a predetermined number; when said number is less than or equal to said predetermined number, comparing priorities of said first processor and said plurality of processors, other than said first processor, requesting access to said system bus; and providing access to said system bus for one of said plurality of processors requesting access to said system bus and having a highest priority.
Claim 29
Dependent Claim
51 words
The bus arbitration method as claimed in claim 22, further comprising a step of generating a waiting signal for delaying arbitration of another one of said plurality of processors requesting access to said system bus while said one of said plurality of processors having said highest priority accesses said system bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-20 | 2001-04-21 | 2001-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-20 | 2005-04-21 | 2005-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-20 | 2009-04-21 | 2009-10-21 | $7700.00 | Window Closed / Lapsed |