US5677637A
Expired / Lapsed
US
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Logic device using single electron coulomb blockade techniques
Assignee: Hitachi Ltd
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Filing: 1996-02-27
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Granted: 1997-10-14
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Expires: 2016-02-27
Abstract
Abstract A memory device includes a memory node (2) to which is connected a tunnel barrier configuration such that the node exhibits first and second quantized memory states for which the level of stored charge is limited by Coulomb Blockade and a surplus or shortfall of a small number of electrons for example ten electrons or even a single electron can be used to represent quantized memory states. A series of the nodes N0-N3 that are interconnected by tunnel barriers D can be arranged as a logic device. Clock waveforms V1-V3 applied to clock lines C1 1-C1 3 selectively alter the probability of charge carriers passing through the tunnel diodes D from node to node. An output device, typically a Coulomb blockade electrometer provides an output logical signal indicative of the logical state of node N3. Arrays of separately addressable memory cells M mn are also described, that utilize gated multiple tunnel junctions (MTJs) as their barrier configurations. Side gated GaAs MTJ structures formed by selective etching and lithography are described. Also, gate structures which modulate a conductive channel with depletion regions to form multiple tunnel junctions are disclosed.
Inventors
- 👤 Kazuo Nakazato
- 👤 Haroon Ahmed
- 👤 Julian D. White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:31
CPC Classifications
B; B82; B82Y; B82Y10/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/56; G11C19/00; G11C19/18; G11C19/182; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; G01; G01R; G01R29/00; G01R29/12; G11C2216/00; G11C2216/02; G11C2216/08; Y; Y10; Y10S; Y10S977/00; Y10S977/902; Y10S977/932; Y10S977/936; Y10S977/937
Claims Analysis
Total Claims: 54
Claim 1
Independent Claim
71 words
A logic device comprising: a charge storage node; barrier means; means for selectively controlling charge carriers passing through the barrier means to the node during a predetermined period, the amount of charge at the node being limited by Coulomb Blockade to thereby define first and second logical states; and output logic means for providing an output logic signal with different logical levels in response to said logical states of the node.
Claim 2
Dependent Claim
71 words
A logic device comprising: a charge storage node; barrier means; means for selectively controlling charge carriers passing through the barrier means to the node during a predetermined period, the amount of charge at the node being limited by Coulomb Blockade to thereby define first and second logical states; and output logic means for providing an output logic signal with different logical levels in response to said logical states of the node.
Claim 3
Dependent Claim
75 words
A logic device comprising: a charge storage node; barrier means; clock means for selectively altering the probability of charge carriers passing through the barrier means to the node during a clocking period, the amount of charge at the node being limited by Coulomb Blockade to thereby define first and second logical states; and output logic means for providing an output logic signal with different logical levels in response to said logical states of the node.
Claim 4
Dependent Claim
75 words
A logic device comprising: a charge storage node; barrier means; clock means for selectively altering the probability of charge carriers passing through the barrier means to the node during a clocking period, the amount of charge at the node being limited by Coulomb Blockade to thereby define first and second logical states; and output logic means for providing an output logic signal with different logical levels in response to said logical states of the node.
Claim 5
Dependent Claim
48 words
A device according to claim 2 including logic control means coupled to said clock means for applying a potential to the node to control whether a charge carrier passes through the barrier to the node during the clocking period, to thereby control the logical state of the node.
Claim 6
Dependent Claim
102 words
A device according to claim 2 including a first and a second of said charge storage nodes and a first and a second of said barrier means, the first barrier means being coupled to the first node, and the second barrier means being coupled between first and second nodes, said clocking means including means for cyclicly raising and lowering the probability of charge passing through the barrier means respectively whereby to permit charge to enter the first node through the first barrier means, and to permit charge from the first node to pass through the second barrier means to the second node.
Claim 7
Dependent Claim
35 words
A device according to claim 4 including at least one further barrier means and node serially connected to said second node so that said nodes and said barrier means are serially connected in a line.
Claim 8
Dependent Claim
12 words
A device according to claim 5 including a plurality of said lines.
Claim 9
Dependent Claim
25 words
A device according to claim 6 including means for coupling at least one node of one of the lines to the other of the lines.
Claim 10
Dependent Claim
32 words
A device according to claim 2 including a logical unit comprising said node and at least a further node, and means for transferring the logical state of said unit to another thereof.
Claim 11
Dependent Claim
21 words
A device according to claim 8 including a Coulomb electrometer for detecting the state of at least one of said nodes.
Claim 12
Dependent Claim
26 words
A device according to claim 8 wherein the clock means, includes means for providing a plurality of clocking waveforms to respective nodes of each logic unit.
Claim 13
Dependent Claim
21 words
A device according to claim 10 wherein the means for providing a plurality of clocking wave forms includes a transmission line.
Claim 14
Dependent Claim
16 words
A device according to claim 2 wherein the barrier means comprises at least one tunnel junction.
Claim 15
Dependent Claim
19 words
A device according to claim 2 wherein said barrier means comprises first and second tunnel diodes connected in series.
Claim 16
Dependent Claim
14 words
A device according to claim 1 wherein the barrier means comprises a multiple-tunnel junction.
Claim 17
Dependent Claim
40 words
A device according to claim 2 wherein said node comprises a conductive track formed on a substrate and said barrier means comprises a tunnel diode including a conductive channel overlying said track and spaced therefrom by an electrically insulating region.
Claim 18
Dependent Claim
15 words
A device according to claim 15 including at least one clock line overlying said track.
Claim 19
Dependent Claim
98 words
A memory device including a memory cell that comprises: a memory node for storing charge; means for providing a tunnel barrier configuration for charge carriers, in a region coupled to the memory node in such a manner that the node exhibits first and second quantized memory states for which the level of stored charge is limited by Coulomb Blockade; gate means for producing a field in said region that controls the tunnel barrier configuration; and control means for controlling charge carrier tunnelling through the tunnel barrier configuration to produce a transition between the quantized states at the node.
Claim 20
Dependent Claim
98 words
A memory device including a memory cell that comprises: a memory node for storing charge; means for providing a tunnel barrier configuration for charge carriers, in a region coupled to the memory node in such a manner that the node exhibits first and second quantized memory states for which the level of stored charge is limited by Coulomb Blockade; gate means for producing a field in said region that controls the tunnel barrier configuration; and control means for controlling charge carrier tunnelling through the tunnel barrier configuration to produce a transition between the quantized states at the node.
Claim 21
Dependent Claim
45 words
A device according to claim 17 including capacitor means coupled to the memory node, the control means including means for applying a voltage across the capacitor means, for controlling charge tunnelling through the barrier means to produce said transition between quantized states at the node.
Claim 22
Dependent Claim
40 words
A device according to claim 17 wherein the control means includes means for controlling the field produced by the gate means, for controlling charge carrier tunnelling through the barrier means to produce said transition between quantized states at the node.
Claim 23
Dependent Claim
20 words
A device according to claim 17 including means for providing a further tunnel barrier configuration coupled to the memory node.
Claim 24
Dependent Claim
21 words
A device according to claim 20 including further gate means for producing a field that influences said further tunnel barrier configuration.
Claim 25
Dependent Claim
25 words
A device according to claim 17 including output means for providing a logical output signal in response to the memory state of the memory node.
Claim 26
Dependent Claim
13 words
A device according to claim 22 wherein the output means comprises an electrometer.
Claim 27
Dependent Claim
13 words
A device according to claim 17 including a plurality of the memory cells.
Claim 28
Dependent Claim
70 words
A device according to claim 24 wherein the memory cells are arranged in rows and columns, with a plurality of address lines associated with the rows and columns respectively, at least one said cell including first and second means responsive to predetermined combinations of control potentials on the address lines for a row and column associated with the cell, for individually switching the cell between said first and second states.
Claim 29
Dependent Claim
65 words
A device according to claim 25 wherein the cell includes a side gated MTJ with a source-drain path coupled to the memory node, means defining a gate capacitor coupled between the memory node and one of the column and row address lines associated with the cell, the side gate of the MTJ being coupled to the other of the address lines associated with the cell.
Claim 30
Dependent Claim
66 words
A device according to claim 25 wherein the cell includes a side gated MTJ with a source-drain path coupled to the memory node and one of the column and row address lines associated with the cell, the side gate of the MTJ being coupled to the other of the address lines associated with the cell, and means defining a gate capacitor coupled to the memory node.
Claim 31
Dependent Claim
75 words
A device according to claim 25 wherein the cell includes a side gated MTJ with a source-drain path coupled to the memory node, the side gate of the MTJ being coupled to a fixed voltage source, means defining a first gate capacitor coupled between the memory node and the column address line for the cell, and means defining a second gate capacitor coupled between the memory node and the row address line for the cell.
Claim 32
Dependent Claim
71 words
A device according to claim 25 wherein the cell includes a side gated MTJ with a source-drain path coupled to the memory node and one of the column and row address lines for the cell, the side gate of the MTJ being coupled to a fixed voltage source, means defining a gate capacitor coupled between the memory node and the other of the column and row address lines for the cell.
Claim 33
Dependent Claim
83 words
A device according to claim 25 wherein the cell includes first and second side gated MTJs each with a source-drain path coupled to the memory node and their side gates coupled to a fixed voltage source, the source-drain path of one of the MTJs being coupled to one of the column and row address lines associated with the cell, and means defining a gate capacitor coupled between the memory node and the other of the column and row address lines for the cell.
Claim 34
Dependent Claim
34 words
A device according to any one of claim 24 including an output means within each of the cells for providing a logical output signal in response to the memory state of the cells respectively.
Claim 35
Dependent Claim
54 words
A device according to claim 31 wherein each said output means comprises a device with a source-drain path and a gate coupled to the memory node, the array including column and row reading lines, the source-drain path of the output means being coupled between the column and row reading lines associated with the cell.
Claim 36
Dependent Claim
32 words
A device according to claim 32 wherein the output means comprises a side gated MTJ whereby the source-drain current thereof is modulated in dependence upon the memory state of the memory node.
Claim 37
Dependent Claim
13 words
A device according to claim 32 wherein the output means comprises a FET.
Claim 38
Dependent Claim
23 words
A device according to claim 32 including means for applying selective reading address signals to the reading lines to address the cells individually.
Claim 39
Dependent Claim
49 words
A device according to claim 17 wherein the means providing the tunnel barrier configuration includes a conductive channel that has been formed by selective etching and lithography from a δ-doped layer in a substrate, the channel including a region of constricted width which exhibits the characteristics of a MTJ.
Claim 40
Dependent Claim
14 words
A device according to claim 36 including side gate means adjacent the constricted region.
Claim 41
Dependent Claim
26 words
A device according to claim 37 wherein the side gate means comprises a portion of the delta doped layer, the portion being spaced from the channel.
Claim 42
Dependent Claim
21 words
A device according to claim 37 wherein the side gate means comprises a further conductive layer disposed vertically within the substrate.
Claim 43
Dependent Claim
53 words
A device according to claim 17 wherein the means for providing the tunnel barrier configuration comprises a source, a drain, a channel extending from the source to the drain, and a side gate that includes a plurality of regions which induce spaced depletion regions in the channel to provide said tunnel barrier configuration.
Claim 44
Dependent Claim
13 words
A device according to claim 40 wherein the gate regions comprise spaced digitations.
Claim 45
Dependent Claim
15 words
A device according to claim 40 wherein the gate regions comprise spaced gate thickness modulations.
Claim 46
Dependent Claim
106 words
A memory device including: a memory node for storing charge; means for providing a barrier configuration for charge carriers, coupled to the memory node, in such a manner that the node exhibits first and second quantized memory states for which the level of stored charge is limited by Coulomb Blockade; and control means for controlling charge carrier tunnelling through the barrier configuration to produce a transition between the quantized states at the node, including first and second means for applying respective control potentials to the barrier configuration, the node being switched between said first and second states in response to predetermined combinations of said control potentials.
Claim 47
Dependent Claim
106 words
A memory device including: a memory node for storing charge; means for providing a barrier configuration for charge carriers, coupled to the memory node, in such a manner that the node exhibits first and second quantized memory states for which the level of stored charge is limited by Coulomb Blockade; and control means for controlling charge carrier tunnelling through the barrier configuration to produce a transition between the quantized states at the node, including first and second means for applying respective control potentials to the barrier configuration, the node being switched between said first and second states in response to predetermined combinations of said control potentials.
Claim 48
Dependent Claim
18 words
A device according to claim 43 wherein the means for providing the barrier configuration includes a side gate.
Claim 49
Dependent Claim
16 words
A device according to claim 43 wherein the barrier configuration comprises a multiple tunnel junction device.
Claim 50
Dependent Claim
70 words
A memory device including: a memory node for storing charge; a plurality of tunnel Junction barriers, serially coupled to the memory node such that the node exhibits bistable quantized memory states for which the level of stored charge is limited by Coulomb Blockade; and control means for selectively controlling charge carrier tunnelling through a plurality of tunnel barriers to produce a transition between the bistable quantized states and the node.
Claim 51
Dependent Claim
70 words
A memory device including: a memory node for storing charge; a plurality of tunnel Junction barriers, serially coupled to the memory node such that the node exhibits bistable quantized memory states for which the level of stored charge is limited by Coulomb Blockade; and control means for selectively controlling charge carrier tunnelling through a plurality of tunnel barriers to produce a transition between the bistable quantized states and the node.
Claim 52
Dependent Claim
19 words
A device according to claim 46 wherein the plurality of tunnel junction barriers comprises a multiple tunnel junction device.
Claim 53
Dependent Claim
15 words
A device according to claim 47 wherein the multiple tunnel device includes a side gate.
Claim 54
Dependent Claim
17 words
A device according to claim 46 including an electrometer for sensing the state of the memory node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-13 | 2001-04-14 | 2001-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-13 | 2005-04-14 | 2005-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-13 | 2009-04-14 | 2009-10-14 | $7700.00 | Window Closed / Lapsed |