Semiconductor package having semiconductor chip mounted on board in face-down relation

Claim 2

A semiconductor package, comprising: a board having a wiring circuit including a connecting portion on a first main surface; a semiconductor chip mounted on the first main surface of said board in face-down relation; a resin layer filled into a space formed between a surface of said semiconductor chip and the first main surface of said board; flat type external connecting terminals electrically connected to said semiconductor chip and formed on a second main surface of said board; and a dummy wiring pattern formed along an outer peripheral edge portion of at least one of the first main surface of said board and an inner wiring layer of said board, the dummy wiring pattern surrounding an inner area of the board.

Claim 3

The semiconductor package as set forth in claim 1, wherein the connecting portion of said board and an electrode portion of said semiconductor chip cover a part of said outer peripheral edge portion that is significant for shielding.

Claim 4

The semiconductor package as set forth in claim 1 or 2, wherein said dummy wiring pattern lies along the outer peripheral edge with a width of 2 mm or less.

Claim 5

A semiconductor package, comprising: a board having a wiring circuit including a connecting portion on a first main surface; a semiconductor chip mounted on the first main surface of said board in face-down relation; a resin layer filled into a space formed between a surface of said semiconductor chip and the first main surface of said board; flat type external connecting terminals electrically connected to said semiconductor chip and formed on a second main surface of said board with constant pitches in a lattice shape; and a dummy wiring pattern formed along an outer peripheral edge portion of at least one of the first main surface of said board and an inner wiring layer, the dummy wiring pattern surrounding an inner area of the board.

Claim 6

A semiconductor package, comprising: a board having a wiring circuit including a connecting portion on a first main surface; a semiconductor chip mounted on the first main surface of said board in face-down relation; a resin layer filled into a space formed between a surface of said semiconductor chip and the first main surface of said board; flat type external connecting terminals electrically connected to said semiconductor chip and formed on a second main surface of said board with constant pitches in a lattice shape; and a dummy wiring pattern formed along an outer peripheral edge portion of at least one of the first main surface of said board and an inner wiring layer, the dummy wiring pattern surrounding an inner area of the board.

Claim 7

The semiconductor package as set forth in claim 4, wherein the connecting portion of said board and an electrode portion of said semiconductor chip cover a part of said outer peripheral edge portion that is significant for shielding.

Claim 8

The semiconductor package as set forth in claim 4 or 5, wherein said dummy wiring pattern is formed along the outer peripheral edge with a width of 2 mm or less.

Claim 9

A semiconductor package, comprising: a board having a wiring circuit including a connecting portion and a dummy non-connecting portion on a first main surface; a semiconductor chip mounted on the first main surface of said board in face-down relation; a resin layer filled into a space formed between a surface of said semiconductor chip and the first main surface of said board; and flat type external connecting terminals electrically connected to said semiconductor chip and formed on a second main surface of said board, wherein the wiring circuit including the connecting portion formed on a wiring portion of the first main surface of said board is substantially formed on the same plane as said dummy non-connecting portion of the first main surface of said board.

Claim 10

A semiconductor package, comprising: a board having a wiring circuit including a connecting portion and a dummy non-connecting portion on a first main surface; a semiconductor chip mounted on the first main surface of said board in face-down relation; a resin layer filled into a space formed between a surface of said semiconductor chip and the first main surface of said board; and flat type external connecting terminals electrically connected to said semiconductor chip and formed on a second main surface of said board, wherein the wiring circuit including the connecting portion formed on a wiring portion of the first main surface of said board is substantially formed on the same plane as said dummy non-connecting portion of the first main surface of said board.

Claim 11

The semiconductor package as set forth in claim 7, wherein the flatness of the plane of the wiring circuit including the connecting, portion of the first main surface to that of the dummy non-connecting portion of the first main surface of said board is ±10 μm.

Claim 12

The semiconductor package as set forth in claim 7 or 8, wherein the dummy non-connecting portion comprises a dummy wiring pattern formed along an outer peripheral edge portion of said circuit, the dummy wiring pattern surrounding an inner area of the board.

Claim 13

The semiconductor package as set forth in claim 7, wherein said flat type external connecting terminals are electrically connected to said semiconductor chip and formed on the second main surface of said board by filled-via-hole connections.

Claim 14

The semiconductor package as set forth in claim 10, wherein the flatness of the plane of the wiring circuit including the connecting portion of the first main surface to that of the dummy non-connecting portion of the first main surface of said board is ±10 μm.

Claim 15

The semiconductor package as set forth in claim 10 or 11, wherein the dummy non-connecting portion comprises a dummy wiring pattern formed along an outer peripheral edge portion of said circuit, the dummy wiring pattern surrounding an inner area of the board.

Claim 16

A semiconductor package, comprising: a board having a wiring circuit including a connecting portion on a first main surface; a semiconductor chip mounted on the first main surface of said board in face-down relation; a resin layer filled into a space formed between a surface of said semiconductor chip and the first main surface of said board; flat type external connecting terminals electrically connected to said semiconductor chip and formed on a second main surface of said board; and a dummy wiring pattern formed along an outer peripheral edge portion of at least one of the first main surface of said board and an inner wiring layer of said board so that the dummy wiring pattern prevents the semiconductor chip from being affected by noise.

Claim 17

A semiconductor package, comprising: a board having a wiring circuit including a connecting portion on a first main surface; a semiconductor chip mounted on the first main surface of said board in face-down relation; a resin layer filled into a space formed between a surface of said semiconductor chip and the first main surface of said board; flat type external connecting terminals electrically connected to said semiconductor chip and formed on a second main surface of said board; and a dummy wiring pattern formed along an outer peripheral edge portion of at least one of the first main surface of said board and an inner wiring layer of said board so that the dummy wiring pattern prevents the semiconductor chip from being affected by noise.

Claim 18

A semiconductor package, comprising: a board having a wiring circuit including a connecting portion on a first main surface; a semiconductor chip mounted on the first main surface of said board in face-down relation; a resin layer filled into a space formed between a surface of said semiconductor chip and the first main surface of said board; flat type external connecting terminals electrically connected to said semiconductor chip and formed on a second main surface of said board with constant pitches in a lattice shape; a dummy wiring pattern formed along an outer peripheral edge portion of at least one of the first main surface of said board and an inner wiring layer of said board so that the dummy wiring pattern prevents the semiconductor chip from being affected by noise.

Claim 19

A semiconductor package, comprising: a board having a wiring circuit including a connecting portion on a first main surface; a semiconductor chip mounted on the first main surface of said board in face-down relation; a resin layer filled into a space formed between a surface of said semiconductor chip and the first main surface of said board; flat type external connecting terminals electrically connected to said semiconductor chip and formed on a second main surface of said board with constant pitches in a lattice shape; a dummy wiring pattern formed along an outer peripheral edge portion of at least one of the first main surface of said board and an inner wiring layer of said board so that the dummy wiring pattern prevents the semiconductor chip from being affected by noise.

Claim 20

A semiconductor package, comprising: a board having a wiring circuit including a connecting portion on a first main surface; a semiconductor chip mounted on the first main surface of said board in face-down relation, the semiconductor chip having a connecting portion on a surface which is opposed to the first main surface of the board; connecting bumps connecting the connecting portion of the board and the connecting portion of the semiconductor chip, and all of connecting bumps being of like size and of like material; a resin layer filled into a space formed between a surface of said semiconductor chip and the first main surface of said board; flat type external connecting terminals electrically connected to said semiconductor chip and formed on a second main surface of said board; and a dummy wiring pattern formed along an other peripheral edge portion of at least one of the first main surface of said board and an inner wiring layer of said board.

Claim 21

A semiconductor package, comprising: a board having a wiring circuit including a connecting portion on a first main surface; a semiconductor chip mounted on the first main surface of said board in face-down relation, the semiconductor chip having a connecting portion on a surface which is opposed to the first main surface of the board; connecting bumps connecting the connecting portion of the board and the connecting portion of the semiconductor chip, and all of connecting bumps being of like size and of like material; a resin layer filled into a space formed between a surface of said semiconductor chip and the first main surface of said board; flat type external connecting terminals electrically connected to said semiconductor chip and formed on a second main surface of said board; and a dummy wiring pattern formed along an other peripheral edge portion of at least one of the first main surface of said board and an inner wiring layer of said board.