US5677228A
Expired / Lapsed
US
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Method of fabricating a resistor in an integrated circuit
Assignee: Vanguard International Semiconductor Corp
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Filing: 1997-01-24
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Granted: 1997-10-14
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Expires: 2017-01-24
Abstract
Abstract A method for forming a resistor in an integrated circuit is disclosed. The method includes forming a composite mask layer on a substrate, and forming a photoresist layer on the composite mask layer to define a trench area. Portions of the composite mask layer and the substrate are then removed using the photoresist layer as an etching mask, thereby forming a trench in the substrate. An isolation oxide layer is conformally formed on the composite mask layer, the sidewalls of the trench, and a bottom of the trench. Further, an undoped polysilicon layer is conformally formed on the isolation oxide layer. Thereafter, a doped polysilicon layer is formed over the undoped polysilicon layer, thereby filling the trench. The doped polysilicon layer is etched back using a first etchant, using the undoped polysilicon layer as an etch stop. The doped polysilicon layer and the undoped polysilicon layer are further etched back using a second etchant different from the first etchant, thereby forming a flat plug, where the second etchant has the same etch rate to both the undoped polysilicon layer and the doped polysilicon layer. Finally, the undoped polysilicon and the doped polysilicon layer are annealed to diffuse dopants of the doped polysilicon layer into the undoped polysilicon layer.
Inventors
- 👤 Horng-Huei Tseng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:11
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; Y; Y10; Y10S; Y10S148/00; Y10S148/036
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
217 words
A method of fabricating a resistor in an integrated circuit, said method comprising the steps of: forming a composite mask layer on a substrate; forming a photoresist layer on the composite mask layer, said photoresist layer defining a trench area on said composite mask layer; removing portions of said composite mask layer and the substrate using said photoresist layer as a mask, thereby forming a trench in the substrate; conformally forming an isolation oxide layer on the composite mask layer, the sidewalls of the trench, and a bottom of the trench; conformally forming an undoped polysilicon layer on said isolation oxide layer; forming a doped polysilicon layer over said undoped polysilicon layer, thereby filling the trench; etching back said doped polysilicon layer using a first etchant, said undoped polysilicon layer being an etch stop; etching back said doped polysilicon layer and said undoped polysilicon layer using a second etchant different from the first etchant, thereby forming a plug comprising said doped polysilicon layer and said undoped polysilicon layer, said plug having a flat surface, and the second etchant having the same etching rate to both said undoped polysilicon layer and said doped polysilicon layer; and annealing said undoped polysilicon and said doped polysilicon layer, thereby diffusing dopants of said doped polysilicon layer into said undoped polysilicon layer.
Claim 2
Independent Claim
217 words
A method of fabricating a resistor in an integrated circuit, said method comprising the steps of: forming a composite mask layer on a substrate; forming a photoresist layer on the composite mask layer, said photoresist layer defining a trench area on said composite mask layer; removing portions of said composite mask layer and the substrate using said photoresist layer as a mask, thereby forming a trench in the substrate; conformally forming an isolation oxide layer on the composite mask layer, the sidewalls of the trench, and a bottom of the trench; conformally forming an undoped polysilicon layer on said isolation oxide layer; forming a doped polysilicon layer over said undoped polysilicon layer, thereby filling the trench; etching back said doped polysilicon layer using a first etchant, said undoped polysilicon layer being an etch stop; etching back said doped polysilicon layer and said undoped polysilicon layer using a second etchant different from the first etchant, thereby forming a plug comprising said doped polysilicon layer and said undoped polysilicon layer, said plug having a flat surface, and the second etchant having the same etching rate to both said undoped polysilicon layer and said doped polysilicon layer; and annealing said undoped polysilicon and said doped polysilicon layer, thereby diffusing dopants of said doped polysilicon layer into said undoped polysilicon layer.
Claim 3
Dependent Claim
33 words
The method according to claim 1, further comprising the steps of: removing a portion of said isolation oxide layer until the surface of the plug is reached; and removing said composite mask layer.
Claim 4
Dependent Claim
45 words
The method according to claim 1, wherein the step of forming said composite mask layer comprises: forming a pad oxide layer on the substrate; forming a silicon oxide layer on said pad oxide layer; and forming a silicon nitride layer on said silicon oxide layer.
Claim 5
Dependent Claim
18 words
The method according to claim 1, wherein the thickness of said undoped polysilicon layer is about 500˜2000 angstroms.
Claim 6
Dependent Claim
20 words
The method according to claim 1, wherein the concentration of said doped polysilicon layer is about 5E20˜1E21 atoms/cm 2 .
Claim 7
Dependent Claim
14 words
The method according to claim 1, wherein said first etchant comprises SF 6 .
Claim 8
Dependent Claim
14 words
The method according to claim 1, wherein said second etchant comprises CF 4 .
Claim 9
Independent Claim
240 words
A method of fabricating a resistor in an integrated circuit, said method comprising: forming a pad oxide layer on a substrate; forming a silicon oxide layer on said pad oxide layer; forming a silicon nitride layer on said silicon oxide layer; forming a photoresist layer on the silicon nitride layer, said photoresist layer defining a trench area on said silicon nitride layer; removing portions of said pad oxide layer, said silicon oxide layer, said silicon nitride layer and the substrate using said photoresist layer as a mask, thereby forming a trench in the substrate; conformally forming an isolation oxide layer on the silicon nitride layer, the sidewalls of the trench, and a bottom of the trench; conformally forming an undoped polysilicon layer on said isolation oxide layer; forming a doped polysilicon layer over said undoped polysilicon layer, thereby filling the trench; etching back said doped polysilicon layer using etchant SF 6 , said undoped polysilicon layer being an etch stop; etching back said doped polysilicon layer and said undoped polysilicon layer using etchant CF 4 , thereby forming a plug comprising said doped polysilicon layer and said undoped polysilicon layer, said plug having a flat surface, and the etchant CF 4 having the same etch rate to both said undoped polysilicon layer and said doped polysilicon layer; and annealing said undoped polysilicon and said doped polysilicon layer, thereby diffusing dopants of said doped polysilicon layer into said undoped polysilicon layer.
Claim 10
Independent Claim
240 words
A method of fabricating a resistor in an integrated circuit, said method comprising: forming a pad oxide layer on a substrate; forming a silicon oxide layer on said pad oxide layer; forming a silicon nitride layer on said silicon oxide layer; forming a photoresist layer on the silicon nitride layer, said photoresist layer defining a trench area on said silicon nitride layer; removing portions of said pad oxide layer, said silicon oxide layer, said silicon nitride layer and the substrate using said photoresist layer as a mask, thereby forming a trench in the substrate; conformally forming an isolation oxide layer on the silicon nitride layer, the sidewalls of the trench, and a bottom of the trench; conformally forming an undoped polysilicon layer on said isolation oxide layer; forming a doped polysilicon layer over said undoped polysilicon layer, thereby filling the trench; etching back said doped polysilicon layer using etchant SF 6 , said undoped polysilicon layer being an etch stop; etching back said doped polysilicon layer and said undoped polysilicon layer using etchant CF 4 , thereby forming a plug comprising said doped polysilicon layer and said undoped polysilicon layer, said plug having a flat surface, and the etchant CF 4 having the same etch rate to both said undoped polysilicon layer and said doped polysilicon layer; and annealing said undoped polysilicon and said doped polysilicon layer, thereby diffusing dopants of said doped polysilicon layer into said undoped polysilicon layer.
Claim 11
Dependent Claim
41 words
The method according to claim 8, further comprising the steps of: removing portion of said isolation oxide layer until the surface of the plug is reached; and removing said silicon nitride layer, said silicon oxide layer, and said pad oxide layer.
Claim 12
Dependent Claim
18 words
The method according to claim 8, wherein the thickness of said undoped polysilicon layer is about 500˜2000 angstroms.
Claim 13
Dependent Claim
20 words
The method according to claim 8, wherein the concentration of said doped polysilicon layer is about 5E20˜1E21 atoms/cm 2 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-10-13 | 2001-04-14 | 2001-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-13 | 2005-04-14 | 2005-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-13 | 2009-04-14 | 2009-10-14 | $7700.00 | Window Closed / Lapsed |