US5675536A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flash memory device
Assignee: SK Hynix Inc
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Filing: 1995-12-21
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Granted: 1997-10-07
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Expires: 2015-12-21
Abstract
Abstract The present invention discloses a flash memory cell which can prevent an over programming in a way that uses a cross coupled latch circuit and peripheral circuits upon a byte programming into a flash memory cell programmed by hot electron injection.
Inventors
- 👤 Hyun Soo Sim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:06
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3468; G11C16/3486; G11C16/10; G11C16/3454; G11C16/3459
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
199 words
A flash memory device, comprising: a first switching means for supplying a latched program data signal to a first node according to a program data input signal; a second switching means for supplying a power supply voltage to a second node based on a program verification enable signal; a third switching means for supplying a drain voltage when programming to a third node based on a program enable-bar signal; a fourth switching means for supplying a ground potential to a fourth node based on said program enable-bar signal; a cross coupled latch circuit coupled between said third node and said fourth node, for latching said drain voltage or said power supply voltage in said first and second nodes based on the switching of said first, second, third and fourth switching means; a fifth switching means for supplying said drain voltage of said first node to a fifth node based on said program enable-bar signal; a column decoder for supplying said drain voltage via said fifth switching means to a selected memory cell based on column decoder signals; and a sixth switching means for supplying said power supply voltage to said fifth node according to said program verification enable signal.
Claim 2
Dependent Claim
199 words
A flash memory device, comprising: a first switching means for supplying a latched program data signal to a first node according to a program data input signal; a second switching means for supplying a power supply voltage to a second node based on a program verification enable signal; a third switching means for supplying a drain voltage when programming to a third node based on a program enable-bar signal; a fourth switching means for supplying a ground potential to a fourth node based on said program enable-bar signal; a cross coupled latch circuit coupled between said third node and said fourth node, for latching said drain voltage or said power supply voltage in said first and second nodes based on the switching of said first, second, third and fourth switching means; a fifth switching means for supplying said drain voltage of said first node to a fifth node based on said program enable-bar signal; a column decoder for supplying said drain voltage via said fifth switching means to a selected memory cell based on column decoder signals; and a sixth switching means for supplying said power supply voltage to said fifth node according to said program verification enable signal.
Claim 3
Dependent Claim
32 words
A flash memory device set forth in claim 1, wherein said first switching means comprises a NMOS transistor for switching said latched program data signal based on said program data input signal.
Claim 4
Dependent Claim
31 words
A flash memory device set forth in claim 1, wherein said second switching means comprises a NMOS transistor for switching said power supply voltage based on said program verification enable signal.
Claim 5
Dependent Claim
29 words
A flash memory device set forth in claim 1, wherein said third switching means comprises a PMOS transistor for switching said drain voltage based on said program enable-bar signal.
Claim 6
Dependent Claim
29 words
A flash memory device set forth in claim 1, wherein said fourth switching means comprises a NMOS transistor for switching said ground voltage based on said program enable-bar signal.
Claim 7
Dependent Claim
33 words
A flash memory device set forth in claim 1, wherein said fifth switching means comprises a PMOS transistor for supplying said drain voltage to said fifth node based on said program enable-bar signal.
Claim 8
Dependent Claim
35 words
A flash memory device set forth in claim 1, wherein said sixth switching means comprises a NMOS transistor for supplying said power supply voltage to said fifth node based on said program verification enable signal.
Claim 9
Dependent Claim
27 words
A flash memory device set forth in claim 1, wherein said column decoder comprises a plurality of PMOS transistors to which each column decoder signal is input.
References Cited (Backward Citations)
JPS5961072A
Cited
US5243573A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-06 | 2001-04-07 | 2001-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-06 | 2005-04-07 | 2005-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-06 | 2009-04-07 | 2009-10-07 | $7700.00 | Window Closed / Lapsed |