FET with stable threshold voltage and method of manufacturing the same

Claim 2

A field effect transistor having stable threshold voltage comprising: a substrate region of a semiconductor material of a first conductivity type and having a surface; a source region of a second conductivity type formed in the substrate region and adjacent to a channel region; a first implant region disposed in the substrate region such that first implant region is contiguous with the source region at the surface and extends into the channel region below the surface of the substrate region, the first implant region having a first concentration of the first conductivity type; and a second implant region disposed between the source region and the first implant region extending beyond the first implant region at the surface and into the channel region, wherein the first implant region and the second implant region form a first dopant profile region of constant doping at an intersection with the source region and in a portion of the substrate region adjacent to the source region, the second implant region having a second concentrating of the first conductivity type.

Claim 3

The field effect transistor having stable threshold voltage of claim 1 wherein the first concentration is approximately 1×10 17 atoms per cm 3 to 1×10 18 atoms per cm 3 .

Claim 4

The field effect transistor having stable threshold voltage of claim 1 wherein the second concentration is approximately 1×10 17 atoms per cm 3 to 1×10 18 atoms per cm 3 .

Claim 5

The field effect transistor having stable threshold voltage of claim 1 further comprising a third implant region disposed between the source region and the first implant region, the third implant region is of the second conductivity type.

Claim 6

The field effect transistor having stable threshold voltage of claim 4 wherein the third implant region has a surface concentration of approximately 1×10 20 atoms per cm.

Claim 7

The field effect transistor having stable threshold voltage of claim 1 further comprising: a drain region of the second conductivity type formed in the substrate region; a third implant region disposed below the drain region and extending into a channel side of the drain region, the third implant region having a third concentration of the first conductivity type; and a fourth implant region disposed between the drain region and the third implant region and extending into the channel side of the drain region, wherein the third and fourth implant regions form a second dopant profile region of constant doping at an intersection with the drain region a portion of the channel region adjacent to the drain region, the fourth implant region having a fourth concentration of the first conductivity type.

Claim 8

The field effect transistor having stable threshold voltage of claim 6 wherein the third concentration is approximately 1×10 17 atoms per cm 3 to 1×10 18 atoms per cm 3 .

Claim 9

The field effect transistor having stable threshold voltage of claim 6 wherein the fourth concentration is approximately 1×10 17 to 1×10 18 atoms per cm 3 .

Claim 10

The field effect transistor having stable threshold voltage of claim 6 further having a fifth implant region disposed between the drain region and the third implant region, the fifth implant region is of the second conductivity type.

Claim 11

The field effect transistor having stable threshold voltage of claim 9 wherein the fifth implant region has a surface concentration of approximately 1×10 20 atoms per cm 3 .

Claim 12

A low voltage unilateral field effect transistor having a robust threshold voltage and punchthrough resistance provided by a plurality of halo regions comprising: a body of a semiconductor material of a first conductivity type and having a first major surface; a gate structure formed on the first major surface, the gate structure having a first edge and a second edge; a source region of a second conductivity type formed in the body of the semiconductor material contiguous with the first edge of the gate structure and extending from the first major surface; a drain region of said second conductivity type formed in the body of the semiconductor material contiguous with the second edge of the gate structure and extending from the first major surface wherein a portion of the body of semiconductor material separates the source region from the drain region to provide a channel region; a plurality of halo regions of the first conductivity type aligned to the first edge of the gate structure and formed in the body of the semiconductor material such that the plurality of halo regions form a dopant profile that is essentially constant where the dopant profile contacts and is adjacent to the source region; a first electrode coupled to the source region; a second electrode coupled to the drain region; and a third electrode coupled to the gate structure.

Claim 13

A low voltage unilateral field effect transistor having a robust threshold voltage and punchthrough resistance provided by a plurality of halo regions comprising: a body of a semiconductor material of a first conductivity type and having a first major surface; a gate structure formed on the first major surface, the gate structure having a first edge and a second edge; a source region of a second conductivity type formed in the body of the semiconductor material contiguous with the first edge of the gate structure and extending from the first major surface; a drain region of said second conductivity type formed in the body of the semiconductor material contiguous with the second edge of the gate structure and extending from the first major surface wherein a portion of the body of semiconductor material separates the source region from the drain region to provide a channel region; a plurality of halo regions of the first conductivity type aligned to the first edge of the gate structure and formed in the body of the semiconductor material such that the plurality of halo regions form a dopant profile that is essentially constant where the dopant profile contacts and is adjacent to the source region; a first electrode coupled to the source region; a second electrode coupled to the drain region; and a third electrode coupled to the gate structure.

Claim 14

The low voltage unilateral field effect transistor of claim 11 wherein the plurality of halo regions comprises a first halo region with a first peak concentration that extends into the channel region 0.05 μm to 0.25 μm from the first edge of the gate structure.

Claim 15

The low voltage unilateral field effect transistor of claim 12 wherein the plurality of halo regions comprises a second halo region with a second peak concentration that extends into the channel region 0.05 μm to 0.2 μm from the first edge of the gate structure.

Claim 16

The low voltage unilateral field effect transistor of claim 11 wherein the gate structure includes a polycrystalline semiconductor layer formed on a gate dielectric layer.

Claim 17

The low voltage unilateral field effect transistor of claim 11 further comprising a first implant region of the second conductivity type formed in the source region.

Claim 18

The low voltage unilateral field effect transistor of claim 11 wherein the dopant profile has an edge, and the edge of the dopant profile extends into the channel region from a first edge of the gate structure a first lateral distance of 0.05 μm to 0.25 μm.