Apparatus for efficiently accessing graphic data for rendering on a display

Claim 3

An apparatus for rendering a geometric primitive as described in claim 1 further comprising: a scan conversion unit generating a pixel pattern of said geometric primitive based on said slopes generated for each edge of said geometric primitive by said first circuit, said scan conversion unit coupled to said first circuit.

Claim 4

An apparatus for rendering a geometric primitive as described in claim 1 wherein said geometric primitive is a triangle having three vertices.

Claim 5

An apparatus for rendering a geometric primitive as described in claim 3 wherein said predetermined vertex order is based on a screen coordinate value associated with each vertex of said three vertices.

Claim 6

An apparatus for rendering a geometric primitive as described in claim 4 wherein said third circuit further comprises a pointer indicating said predetermined vertex order to said multiplexing circuitry, said pointer communicatively coupled to control said multiplexing circuitry.

Claim 7

An apparatus for rendering a geometric primitive as described in claim 4 wherein said screen coordinate value is a Y-axis coordinate value of a computer display screen.

Claim 8

An apparatus for rendering a geometric primitive as described in claim 3 wherein said predetermined vertex order is based on a screen coordinate value associated with each vertex of said three vertices and wherein each signal line coupled to said first circuit corresponds to an individual vertex of said plurality of vertices of said triangle primitive.

Claim 9

An apparatus for rendering a geometric primitive as described in claim 1 wherein said geometric primitive is a quadrilateral having four vertices.

Claim 10

An apparatus for rendering a geometric primitive as described in claim 8 wherein said predetermined vertex order is based on a screen coordinate value associated with each vertex of said four vertices and wherein: said second circuit is also for generating a comparison result between a first dot product of surface normals associated with a first vertex and a third vertex and a second dot product of surface normals associated with a second vertex and a fourth vertex; and wherein said third circuit is also responsive to said second circuit and is also for splitting said quadrilateral primitive into two triangle subprimitives according to said comparison result, wherein said multiplexing circuitry is also for supplying said triangle subprimitives to said first circuit according to said predetermined vertex order.

Claim 11

An apparatus for rendering a geometric primitive as described in claim 9 wherein said predetermined vertex order is based on a screen coordinate value associated with each vertex of said four vertices and further comprising (a) a select indicator for selecting a first triangle subprimitive of said two triangle subprimitives; (b) wherein provided said select indicator selects a first triangle subprimitive: (i) said second circuit generates comparison results of screen coordinate values between pairs of vertices of said first triangle subprimitive; (ii) said third circuit orders said vertices of said first triangle subprimitive according to said comparison results of screen coordinate values between pairs of vertices of said first triangle subprimitive; and (iii) a pointer indicates said predetermined vertex order to control said multiplexing circuitry based on said first triangle; and (c) wherein provided said select indicator selects a second triangle subprimitive: (i) said second circuit generates comparison results of screen coordinate values between pairs of vertices of said second triangle subprimitive; (ii) said third circuit orders said vertices of said second triangle subprimitive according to said comparison results of screen coordinate values between pairs of vertices of said second triangle subprimitive; and (iii) said pointer indicates said predetermined vertex order to control said multiplexing circuitry based on said second triangle subprimitive.

Claim 12

In a computer controlled graphics system including a display displaying computer generated images and a memory unit storing information representing geometric primitives, an apparatus for rendering said geometric primitives onto said display, said apparatus comprising: a plurality of processors coupled to a common instruction bus according to a SIMD architecture, each processor simultaneously processing a separate geometric primitive, each processor further comprising: a plurality of memory units for storing information representing said geometric primitive wherein information associated with each vertex of said geometric primitive is stored in a separate memory unit; a mathematical processing circuit processing said information representing said geometric primitive in a predetermined vertex ordering to provide display information regarding said geometric primitive; multiplexing circuitry coupled to said plurality of memory units and coupled to said mathematical processing circuit, said multiplexing circuitry simultaneously providing said information representing said geometric primitive from said plurality of memory units to said mathematical unit in said predetermined vertex ordering; and vertex order determining circuitry determining a vertex ordering of said geometric primitive and generating output pointers indicative of said vertex ordering, said vertex order determining circuitry coupled to receive comparison signals indicating results of comparisons of parameters associated with pairs of said vertices of said geometric primitive.

Claim 13

In a computer controlled graphics system including a display displaying computer generated images and a memory unit storing information representing geometric primitives, an apparatus for rendering said geometric primitives onto said display, said apparatus comprising: a plurality of processors coupled to a common instruction bus according to a SIMD architecture, each processor simultaneously processing a separate geometric primitive, each processor further comprising: a plurality of memory units for storing information representing said geometric primitive wherein information associated with each vertex of said geometric primitive is stored in a separate memory unit; a mathematical processing circuit processing said information representing said geometric primitive in a predetermined vertex ordering to provide display information regarding said geometric primitive; multiplexing circuitry coupled to said plurality of memory units and coupled to said mathematical processing circuit, said multiplexing circuitry simultaneously providing said information representing said geometric primitive from said plurality of memory units to said mathematical unit in said predetermined vertex ordering; and vertex order determining circuitry determining a vertex ordering of said geometric primitive and generating output pointers indicative of said vertex ordering, said vertex order determining circuitry coupled to receive comparison signals indicating results of comparisons of parameters associated with pairs of said vertices of said geometric primitive.

Claim 14

An apparatus as described in claim 11 further comprising a scan conversion unit accessing said display information regarding said geometric primitive for said each processor and generating therefrom a pixel pattern representative of said geometric primitive for each processor, said scan conversion unit coupled to each processor and coupled to said display.

Claim 15

An apparatus as described in claim 11 wherein said plurality of processors comprise at least four processors.

Claim 16

An apparatus as described in claim 11 wherein said comparisons of parameters associated with said vertices comprise comparisons of screen coordinate values associated with each of said vertices.

Claim 17

An apparatus as described in claim 11 further comprising: geometric primitive splitting signal for splitting a geometric primitive into first and second geometric primitives and for indicating a split direction; and a combination circuit for generating select signals to instruct said multiplexing circuitry to couple said plurality of memory units to said mathematical processing circuit to realize said predetermined vertex ordering for said first geometric primitive or said second geometric primitive based on said vertex ordering and said split direction, said combination circuit communicatively coupled to said multiplexing circuitry and to said vertex order determining circuitry.

Claim 18

An apparatus as described in claim 15 wherein said first and said second geometric primitive are triangles.

Claim 19

An apparatus as described in claim 15 wherein said vertex order determining circuitry operates on a triangle primitive and said geometric primitive splitting signal operates on a quadrilateral primitive to form two triangle primitives.

Claim 20

In a computer controlled graphics system including a display displaying computer generated images and a memory unit storing information representing geometric primitives, an apparatus for rendering said geometric primitives onto said display, said apparatus comprising: a plurality of processors coupled to a common instruction bus according to a SIMD architecture, each processor simultaneously processing a separate geometric primitive, each processor further comprising: a first circuit determining slopes based on said information associated with said plurality of vertices of said geometric primitive, each slope associated with an edge of said geometric primitive, said first circuit processing said information associated with said plurality of vertices in a predetermined vertex order, said first circuit coupled to a plurality of signal lines for receiving said information; a plurality of memories for storing said information associated with said plurality of vertices, each memory for storing information associated with a separate vertex of said geometric primitive and each memory having a separate output line; multiplexing circuitry coupled to said plurality of memories and coupled to said first circuit for intercoupling an output line of each memory to an individual signal line of said plurality of signal lines coupled to said first circuit wherein said multiplexing circuitry simultaneously supplies said information associated with said plurality of vertices from said plurality of memories to said first circuit in said predetermined vertex order; a second circuit generating comparison results of screen coordinate values between pairs of vertices of said geometric primitive; and a third circuit ordering said plurality of vertices of said geometric primitive according to said predetermined vertex order, said third circuit coupled to receive said comparison results from said second circuit and coupled to control said multiplexing circuitry.

Claim 21

In a computer controlled graphics system including a display displaying computer generated images and a memory unit storing information representing geometric primitives, an apparatus for rendering said geometric primitives onto said display, said apparatus comprising: a plurality of processors coupled to a common instruction bus according to a SIMD architecture, each processor simultaneously processing a separate geometric primitive, each processor further comprising: a first circuit determining slopes based on said information associated with said plurality of vertices of said geometric primitive, each slope associated with an edge of said geometric primitive, said first circuit processing said information associated with said plurality of vertices in a predetermined vertex order, said first circuit coupled to a plurality of signal lines for receiving said information; a plurality of memories for storing said information associated with said plurality of vertices, each memory for storing information associated with a separate vertex of said geometric primitive and each memory having a separate output line; multiplexing circuitry coupled to said plurality of memories and coupled to said first circuit for intercoupling an output line of each memory to an individual signal line of said plurality of signal lines coupled to said first circuit wherein said multiplexing circuitry simultaneously supplies said information associated with said plurality of vertices from said plurality of memories to said first circuit in said predetermined vertex order; a second circuit generating comparison results of screen coordinate values between pairs of vertices of said geometric primitive; and a third circuit ordering said plurality of vertices of said geometric primitive according to said predetermined vertex order, said third circuit coupled to receive said comparison results from said second circuit and coupled to control said multiplexing circuitry.

Claim 22

An apparatus as described in claim 18 further comprising: a scan conversion unit generating a pixel pattern of said geometric primitive based on said slopes generated for each edge of said geometric primitive by said first circuit, said scan conversion unit coupled to said first circuit.

Claim 23

An apparatus as described in claim 18 wherein said predetermined vertex order is based on a screen coordinate value associated with each vertex of said three vertices.

Claim 24

An apparatus as described in claim 18 wherein said third circuit further comprises a pointer indicating said predetermined vertex order to said multiplexing circuitry, said pointer communicatively coupled to control said multiplexing circuitry.

Claim 25

An apparatus for rendering a geometric primitive as described in claim 18 wherein said predetermined vertex order is based on a screen coordinate value associated with each vertex of four vertices and wherein: said second circuit is also for generating a comparison result between a first dot product of surface normals associated with a first vertex and a third vertex and a second dot product of surface normals associated with a second vertex and a fourth vertex; and wherein said third circuit is also responsive to said second circuit and is also for splitting a quadrilateral primitive into two triangle subprimitives according to said comparison result, wherein said multiplexing circuitry is also for supplying said triangle subprimitives to said first circuit according to said predetermined vertex order.