Duplicated arrangement for ATM switching system

Claim 2

A switching arrangement for an asynchronous transfer mode (ATM) switching system, comprising: first and second store-and-forward buffers for storing and forwarding an ATM cell stream; a timing signal generator; first and second counters responsive to said timing signal for producing a first cell count and a second cell count representative of numbers of cells stored in said first and second store-and-forward buffers, respectively; a difference detector for detecting a difference between said first and second cell counts; a controller for controlling said second store-and-forward buffer in accordance with said difference so that said number of cells in said second store-and-forward buffer approaches said number of cells in said first store-and-forward buffer, wherein said controller advances or stops storing and forwarding by said second store-and-forward buffer in accordance with said difference; and a switch for normally coupling said ATM cell stream forwarded from said first store-and-forward buffer to an output port of said ATM switching system and coupling said ATM cell stream forwarded from said second store-and-forward buffer, instead of from said first store-and-forward buffer, to said output port in response to a switching command signal.

Claim 3

A switching arrangement as claimed in claim 1, further comprising a comparator for comparing said first cell count with a threshold value and disabling said controller when said first cell count is smaller than said threshold value.

Claim 4

A switching arrangement for an asynchronous transfer mode (ATM) switching system, comprising: first and second store-and-forward buffers for storing and forwarding an ATM cell stream; a timing signal generator for producing a plurality of timing cells, a mulitplexer for multiplexing said timing cells with ATM cells to produce a multiplexed ATM cell streams, and a timing cell detector for detecting said timing cells multiplexed in said ATM cell stream; first and second cell counters responsive to said timing cells detected by said timing cell detector for producing first cell count and second cell count representative of numbers of cells stored in said first and second store-and-forward buffers, respectively; a difference detector for detecting a difference between said first and second cell counts; a controller for controlling said second store-and-forward buffer in accordance with said difference so that said number of cells in said second store-and-forward buffer approaches said number of cells in said first store-and-forward buffer; and a switch for normally coupling said ATM cell stream forwarded from said first store-and-forward buffer to an output port of said ATM switching system and coupling said ATM cell stream forwarded from said second store-and-forward buffer, instead of from said first store-and-forward buffer, to said output port in response to a switching command signal.

Claim 5

A switching arrangement for an asynchronous transfer mode (ATM) switching system, comprising: first and second store-and-forward buffers for storing and forwarding an ATM cell stream; a timing signal generator for producing a plurality of timing cells, a mulitplexer for multiplexing said timing cells with ATM cells to produce a multiplexed ATM cell streams, and a timing cell detector for detecting said timing cells multiplexed in said ATM cell stream; first and second cell counters responsive to said timing cells detected by said timing cell detector for producing first cell count and second cell count representative of numbers of cells stored in said first and second store-and-forward buffers, respectively; a difference detector for detecting a difference between said first and second cell counts; a controller for controlling said second store-and-forward buffer in accordance with said difference so that said number of cells in said second store-and-forward buffer approaches said number of cells in said first store-and-forward buffer; and a switch for normally coupling said ATM cell stream forwarded from said first store-and-forward buffer to an output port of said ATM switching system and coupling said ATM cell stream forwarded from said second store-and-forward buffer, instead of from said first store-and-forward buffer, to said output port in response to a switching command signal.

Claim 6

A switching arrangement as claimed in claim 3, wherein said first and second store-and-forward buffers are connected together to said multiplexer for storing and forwarding said multiplexed ATM cell stream, said switch being responsive to one of said timing cells forwarded from one of said buffers for coupling said ATM cell stream forwarded from said second store-and-forward buffer to said output port.

Claim 7

A switching arrangement as claimed in claim 3, wherein said timing cell generator produces said timing cells at periodic intervals.

Claim 8

A switching arrangement as claimed in claim 3, wherein said first and second store-and-forward buffers are connected together to said multiplexer for storing and forwarding said ATM cell stream, and said timing cell generator producing said timing cells at periodic intervals, said switch being responsive to a simultaneous presence of one of said timing cells forwarded from one of said buffers and a switching command signal for coupling said ATM cell stream forwarded from said second store-and-forward buffer to said output port.

Claim 9

A switching arrangement as claimed in claim 3, wherein said first and second store-and-forward buffers are connected together to said multiplexer for storing and forwarding said ATM cell stream, and said timing cell generator producing said timing cells at periodic intervals, said switch being responsive to a simultaneous presence of one of said timing cells forwarded from one of said buffers and a switching command signal for coupling said ATM cell stream forwarded from said second store-and-forward buffer to said output port, further comprising a comparator for comparing said first cell count with a threshold value and disabling said controller and said switch when said first cell count is smaller that said threshold value.

Claim 10

An output buffer asynchronous transfer mode (ATM) switching system comprising: a first switching stage for receiving ATM cells from a plurality of input ports; a second switching stage for also receiving ATM cells from said input ports; first switch having a plurality of terminals for normally coupling said ATM cells from said first switching stage to said terminals and coupling said ATM cells from said second switching stage to said terminals, instead of from said first switching stage, in response to a switching command signal; a plurality of first store-and-forward buffers respectively connected to said terminals for storing and forwarding ATM cells from said terminals; a plurality of second store-and-forward buffers respectively connected to said terminals for storing and forwarding ATM cells from said terminals, said second store-and-forward buffers corresponding respectively to said first store-and-forward buffers; a timing signal generator; a plurality of working units associated with said first store-and-forward buffers, respectively, each of said working units including a first counter responsive to said timing signal for producing a first cell count representative of a number of cells stored in an associated store-and-forward buffer; a plurality of spare units associated with said second store-and-forward buffers, respectively, each of said spare units including a second counter responsive to said timing signal for producing a second cell count representative of a number of cells stored in an associated second store-and-forward buffer, a difference detector for detecting a difference between said first and second cell counts, and a controller for controlling the associated second store-and-forward buffer in accordance with said difference so that said number of cells in said corresponding second store-and-forward buffer approaches said number of cells stored in said corresponding first store-and-forward buffer; a plurality of second switches for normally coupling said ATM cell streams forwarded from said first store-and-forward buffers to output ports of said ATM switching system and coupling said ATM cell streams forwarded from said second store-and-forward buffers, instead of from said first store-and-forward buffers, to said output ports in response to said switching command signal.

Claim 11

An output buffer asynchronous transfer mode (ATM) switching system comprising: a first switching stage for receiving ATM cells from a plurality of input ports; a second switching stage for also receiving ATM cells from said input ports; first switch having a plurality of terminals for normally coupling said ATM cells from said first switching stage to said terminals and coupling said ATM cells from said second switching stage to said terminals, instead of from said first switching stage, in response to a switching command signal; a plurality of first store-and-forward buffers respectively connected to said terminals for storing and forwarding ATM cells from said terminals; a plurality of second store-and-forward buffers respectively connected to said terminals for storing and forwarding ATM cells from said terminals, said second store-and-forward buffers corresponding respectively to said first store-and-forward buffers; a timing signal generator; a plurality of working units associated with said first store-and-forward buffers, respectively, each of said working units including a first counter responsive to said timing signal for producing a first cell count representative of a number of cells stored in an associated store-and-forward buffer; a plurality of spare units associated with said second store-and-forward buffers, respectively, each of said spare units including a second counter responsive to said timing signal for producing a second cell count representative of a number of cells stored in an associated second store-and-forward buffer, a difference detector for detecting a difference between said first and second cell counts, and a controller for controlling the associated second store-and-forward buffer in accordance with said difference so that said number of cells in said corresponding second store-and-forward buffer approaches said number of cells stored in said corresponding first store-and-forward buffer; a plurality of second switches for normally coupling said ATM cell streams forwarded from said first store-and-forward buffers to output ports of said ATM switching system and coupling said ATM cell streams forwarded from said second store-and-forward buffers, instead of from said first store-and-forward buffers, to said output ports in response to said switching command signal.

Claim 12

An output buffer ATM switching system as claimed in claim 8, wherein each of said spare units further includes a comparator for comparing said first cell count with a threshold value and disabling said controller when said first cell count is smaller than said threshold value.

Claim 13

An output buffer asynchronous transfer mode (ATM) switching system comprising: a first switching stage for receiving ATM cells from a plurality of input ports; a second switching stage connected in parallel to said first switching stage for receiving ATM cells from said input ports; a first switch having a plurality of terminals for normally coupling said ATM cells from said first switching stage to said terminals and coupling said ATM cells from said second switching stage to said terminals, instead of from said first switching stage, in response to a switching command signal; a plurality of first store-and-forward buffers respectively connected to said terminals for storing and forwarding ATM cells from said terminals; a plurality of second store-and-forward buffers respectively connected to said terminals for storing and forwarding ATM cells from said terminals, said second store-and-forward buffers corresponding respectively to said first store-and-forward buffers; a plurality of working units associated with said first store-and-forward buffers, respectively, each of said working units including a first counter responsive to said timing signal for producing a first cell count representative of a number of cells storing in an associated store-and-forward buffer; a plurality of spare units associated with said second store-and-forward buffers, respectively, each of said spare units including a second counter responsive to said timing signal for producing a second cell count representative of a number of cells stored in an associated second store-and-forward buffer, a difference detector for detecting a difference between said first and second cell counts, and a controller for controlling the associated second store-and-forward buffer in accordance with said difference so that said number of cells in said corresponding second store-and-forward buffer approaches said number of cells in said corresponding first store-and-forward buffer; a timing signal generator for producing a plurality of timing cells; a plurality of multiplexers for multiplexing said timing cell with ATM cell streams from said terminals to produce a plurality of multiplexed ATM cell streams; one of said working and spare units including a timing cell detector for detecting said timing cells multiplexed in said ATM cell streams, said first and second cell counters being responsive to said timing cells detected by said timing cell detecting means for producing said first and second cell counts; and a plurality of second switches for normally coupling said ATM cell streams forwarded from said first store-and-forward buffers to output ports of said ATM switching system and coupling said ATM cell streams forwarded from said second store-and-forward buffers, instead of from said first store-and-forward buffers, to said output ports in response to a switching command signal.

Claim 14

An output buffer asynchronous transfer mode (ATM) switching system comprising: a first switching stage for receiving ATM cells from a plurality of input ports; a second switching stage connected in parallel to said first switching stage for receiving ATM cells from said input ports; a first switch having a plurality of terminals for normally coupling said ATM cells from said first switching stage to said terminals and coupling said ATM cells from said second switching stage to said terminals, instead of from said first switching stage, in response to a switching command signal; a plurality of first store-and-forward buffers respectively connected to said terminals for storing and forwarding ATM cells from said terminals; a plurality of second store-and-forward buffers respectively connected to said terminals for storing and forwarding ATM cells from said terminals, said second store-and-forward buffers corresponding respectively to said first store-and-forward buffers; a plurality of working units associated with said first store-and-forward buffers, respectively, each of said working units including a first counter responsive to said timing signal for producing a first cell count representative of a number of cells storing in an associated store-and-forward buffer; a plurality of spare units associated with said second store-and-forward buffers, respectively, each of said spare units including a second counter responsive to said timing signal for producing a second cell count representative of a number of cells stored in an associated second store-and-forward buffer, a difference detector for detecting a difference between said first and second cell counts, and a controller for controlling the associated second store-and-forward buffer in accordance with said difference so that said number of cells in said corresponding second store-and-forward buffer approaches said number of cells in said corresponding first store-and-forward buffer; a timing signal generator for producing a plurality of timing cells; a plurality of multiplexers for multiplexing said timing cell with ATM cell streams from said terminals to produce a plurality of multiplexed ATM cell streams; one of said working and spare units including a timing cell detector for detecting said timing cells multiplexed in said ATM cell streams, said first and second cell counters being responsive to said timing cells detected by said timing cell detecting means for producing said first and second cell counts; and a plurality of second switches for normally coupling said ATM cell streams forwarded from said first store-and-forward buffers to output ports of said ATM switching system and coupling said ATM cell streams forwarded from said second store-and-forward buffers, instead of from said first store-and-forward buffers, to said output ports in response to a switching command signal.

Claim 15

An output buffer ATM switching system as claimed in claim 10, wherein each of said first store-and-forward buffers and each respective corresponding second store-and-forward buffer are connected together to a respective one of said multiplexers for storing and forwarding a multiplexed ATM cell stream, each of said second switches being responsive to one of said timing cells contained in an ATM cell stream for coupling said ATM cell stream from a corresponding one of said second store-and-forward buffers to a corresponding one of said output ports.

Claim 16

An output buffer ATM switching system as claimed in claim 10, wherein said timing cell generator produces said timing cell at periodic intervals.

Claim 17

A shared buffer asynchronous transfer mode (ATM) switching system comprising: a first multiplexer stage for multiplexing ATM cells from a plurality of input ports; a second multiplexer stage for also multiplexing ATM cells from said input ports; a first switch having a terminal for normally coupling said ATM cells from said first multiplexer stage to said terminal and coupling said ATM cells from said second multiplexer stage to said terminal, instead of from said first multiplexer stage, in response to a switching command signal; a first shared buffer memory for storing and forwarding ATM cells from said terminal; a second shared buffer memory connected to said second multiplexer stage for storing and forwarding ATM cells from said terminal; a first buffer management logic circuit for controlling management of said first shared buffer memory so that a plurality of first logical buffers are formed in said first shared buffer memory for storing ATM cell streams in said first logical buffer and forwarding said ATM streams therefrom; a second buffer management logic circuit for controlling management of said second shared buffer memory so that a plurality of second logical buffers are formed in said second shared buffer memory for storing ATM cell streams in said second logical buffers and forwarding said ATM cell streams therefrom, said second logical buffers corresponding respectively to said first logical buffers; a timing signal generator; a first counter responsive to said timing signal for producing first cell counts, each first cell count representative of a number of cells stored in a corresponding one of said first logical buffers; a second counter responsive to said timing signal for producing second cell counts, each second cell count representative of a number of cells stored in a corresponding one of said second logical buffers; a difference detector for detecting differences between said first cell counts and said second cell counts and controlling said second buffer management logic circuit in accordance with said differences so that said number of cells in said second logical buffers approach said number of cells in said corresponding first logical buffers; a first demultiplexer stage connected to said first shared buffer memory for demultiplexing ATM cells therefrom; a second demultiplexer stage connected to said second shared buffer memory for demulitplexing ATM cells therefrom; a plurality of second switches for normally coupling ATM cell streams from said first demultiplexer stage to output ports of said ATM switching system and coupling ATM cell streams from said second demultiplexer stage, instead of from said first demultiplexer stage, to said output ports in response to said switching command signal.

Claim 18

A shared buffer asynchronous transfer mode (ATM) switching system comprising: a first multiplexer stage for multiplexing ATM cells from a plurality of input ports; a second multiplexer stage for also multiplexing ATM cells from said input ports; a first switch having a terminal for normally coupling said ATM cells from said first multiplexer stage to said terminal and coupling said ATM cells from said second multiplexer stage to said terminal, instead of from said first multiplexer stage, in response to a switching command signal; a first shared buffer memory for storing and forwarding ATM cells from said terminal; a second shared buffer memory connected to said second multiplexer stage for storing and forwarding ATM cells from said terminal; a first buffer management logic circuit for controlling management of said first shared buffer memory so that a plurality of first logical buffers are formed in said first shared buffer memory for storing ATM cell streams in said first logical buffer and forwarding said ATM streams therefrom; a second buffer management logic circuit for controlling management of said second shared buffer memory so that a plurality of second logical buffers are formed in said second shared buffer memory for storing ATM cell streams in said second logical buffers and forwarding said ATM cell streams therefrom, said second logical buffers corresponding respectively to said first logical buffers; a timing signal generator; a first counter responsive to said timing signal for producing first cell counts, each first cell count representative of a number of cells stored in a corresponding one of said first logical buffers; a second counter responsive to said timing signal for producing second cell counts, each second cell count representative of a number of cells stored in a corresponding one of said second logical buffers; a difference detector for detecting differences between said first cell counts and said second cell counts and controlling said second buffer management logic circuit in accordance with said differences so that said number of cells in said second logical buffers approach said number of cells in said corresponding first logical buffers; a first demultiplexer stage connected to said first shared buffer memory for demultiplexing ATM cells therefrom; a second demultiplexer stage connected to said second shared buffer memory for demulitplexing ATM cells therefrom; a plurality of second switches for normally coupling ATM cell streams from said first demultiplexer stage to output ports of said ATM switching system and coupling ATM cell streams from said second demultiplexer stage, instead of from said first demultiplexer stage, to said output ports in response to said switching command signal.

Claim 19

A shared buffer ATM switching system as claimed in claim 13, further comprising comparator for comparing each of said first cell counts with a threshold value and preventing said second buffer management logic from responding to a corresponding one of said differences when one of said first cell counts is smaller than said threshold value.

Claim 20

A shared buffer asynchronous transfer mode (ATM) switching system comprising: a first multiplexer stage for multiplexing ATM cells from a plurality of input ports; a second multiplexer stage for also multiplexing ATM cells from said input ports; a first switch having a terminal for normally coupling said ATM cells from said first multiplexer stage to said terminal and coupling said ATM cells from said second multiplexer stage to said terminal, instead of from said first multiplexer stage, in response to a switching command signal; a first shared buffer memory for storing and forwarding ATM cells from said terminal; a second shared buffer memory connected to said second multiplexer stage for storing and forwarding ATM cells from said terminal; a first buffer management logic circuit for controlling management of said first shared buffer memory so that a plurality of first logical buffers are formed in said first shared buffer memory for storing ATM cell streams in said first logical buffer and forwarding said ATM streams therefrom; a second buffer management logic circuit for controlling management of said second shared buffer memory so that a plurality of second logical buffers are formed in said second shared buffer memory for storing ATM cell streams in said second logical buffers and forwarding said ATM cell streams therefrom, said second logical buffers corresponding respectively to said first logical buffers; a timing signal generator having a timing cell generator for generating a plurality of timing cells; a multiplexer for multiplexing said timing cells with ATM cells from said terminal of said first switch to produce a multiplexed ATM cell stream; and a timing cell detector for detecting a timing cell multiplexed in said ATM cell stream; a first counter responsive to said timing signal for producing first cell counts, each first cell count representative of a number of cells stored in a corresponding one of said first logical buffers; a second counter responsive to said timing signal for producing second cell counts, each second cell count representative of a number of cells stored in a corresponding one of said second logical buffers; said first and second cell counters being responsive to said timing cells detected by said timing cell detector for producing said first and second cell counts a difference detector for detecting differences between said first cell counts and said second cell counts and controlling said second buffer management logic circuit in accordance with said differences so that said number of cells in said second logical buffers approach said number of cells in said corresponding first logical buffers; a first demultiplexer stage connected to said first shared buffer memory for demultiplexing ATM cells therefrom; a second demultiplexer stage connected to said second shared buffer memory for demulitplexing ATM cells therefrom; plurality of second switches for normally coupling ATM cell streams from said first demultiplexer stage to output ports of said ATM switching system and coupling ATM cell streams from said second demultiplexer stage, instead of from said first demultiplexer stage, to said output ports in response to said switching command signal.

Claim 21

A shared buffer asynchronous transfer mode (ATM) switching system comprising: a first multiplexer stage for multiplexing ATM cells from a plurality of input ports; a second multiplexer stage for also multiplexing ATM cells from said input ports; a first switch having a terminal for normally coupling said ATM cells from said first multiplexer stage to said terminal and coupling said ATM cells from said second multiplexer stage to said terminal, instead of from said first multiplexer stage, in response to a switching command signal; a first shared buffer memory for storing and forwarding ATM cells from said terminal; a second shared buffer memory connected to said second multiplexer stage for storing and forwarding ATM cells from said terminal; a first buffer management logic circuit for controlling management of said first shared buffer memory so that a plurality of first logical buffers are formed in said first shared buffer memory for storing ATM cell streams in said first logical buffer and forwarding said ATM streams therefrom; a second buffer management logic circuit for controlling management of said second shared buffer memory so that a plurality of second logical buffers are formed in said second shared buffer memory for storing ATM cell streams in said second logical buffers and forwarding said ATM cell streams therefrom, said second logical buffers corresponding respectively to said first logical buffers; a timing signal generator having a timing cell generator for generating a plurality of timing cells; a multiplexer for multiplexing said timing cells with ATM cells from said terminal of said first switch to produce a multiplexed ATM cell stream; and a timing cell detector for detecting a timing cell multiplexed in said ATM cell stream; a first counter responsive to said timing signal for producing first cell counts, each first cell count representative of a number of cells stored in a corresponding one of said first logical buffers; a second counter responsive to said timing signal for producing second cell counts, each second cell count representative of a number of cells stored in a corresponding one of said second logical buffers; said first and second cell counters being responsive to said timing cells detected by said timing cell detector for producing said first and second cell counts a difference detector for detecting differences between said first cell counts and said second cell counts and controlling said second buffer management logic circuit in accordance with said differences so that said number of cells in said second logical buffers approach said number of cells in said corresponding first logical buffers; a first demultiplexer stage connected to said first shared buffer memory for demultiplexing ATM cells therefrom; a second demultiplexer stage connected to said second shared buffer memory for demulitplexing ATM cells therefrom; plurality of second switches for normally coupling ATM cell streams from said first demultiplexer stage to output ports of said ATM switching system and coupling ATM cell streams from said second demultiplexer stage, instead of from said first demultiplexer stage, to said output ports in response to said switching command signal.

Claim 22

A shared buffer ATM switching system as claimed in claim 15, wherein said first and second shared buffer memories are connected together to said multiplexer for storing a multiplexed ATM call stream in each of the first logical buffers and in each of said second logical buffers and forwarding the stored ATM cell streams therefrom, each of said second switches being responsive to a timing cell contained in an ATM cell stream for coupling an ATM cell strum from second demultiplexer stage to a corresponding one of said output ports.

Claim 23

An output buffer ATM switching system as claimed in claim 15, wherein said timing cell generator produces said timing cell at periodic intervals.

Claim 24

A switching method for an asynchronous transfer mode (ATM) switching system, comprising the steps of: a) storing an ATM cell stream in first and second store-and-forward buffers and forwarding an ATM cell stream form each of the first and second store-and-forward buffers; b) simultaneously producing a first cell count and a second cell count representative of numbers of cells stored in said first and second store-and-forward buffers, respectively; c) detecting a difference between said first and second cell counts; d) controlling said second store-and-forward buffer by advancing or stopping storing and forwarding in said second store-and-forward buffer in accordance with said difference so that the number of cells in said second store-and-forward buffer approaches the number of cells in said first store-and-forward buffer; and e) normally coupling said ATM cell stream forwarded from said first store-and-forward buffer to an output port of said ATM switching system and coupling said ATM stream forwarded from said second store-and-forward buffer, instead of from said first store-and-forward buffer, to said output port in response to a switching command signal.

Claim 25

A switching method for an asynchronous transfer mode (ATM) switching system, comprising the steps of: a) storing an ATM cell stream in first and second store-and-forward buffers and forwarding an ATM cell stream form each of the first and second store-and-forward buffers; b) simultaneously producing a first cell count and a second cell count representative of numbers of cells stored in said first and second store-and-forward buffers, respectively; c) detecting a difference between said first and second cell counts; d) controlling said second store-and-forward buffer by advancing or stopping storing and forwarding in said second store-and-forward buffer in accordance with said difference so that the number of cells in said second store-and-forward buffer approaches the number of cells in said first store-and-forward buffer; and e) normally coupling said ATM cell stream forwarded from said first store-and-forward buffer to an output port of said ATM switching system and coupling said ATM stream forwarded from said second store-and-forward buffer, instead of from said first store-and-forward buffer, to said output port in response to a switching command signal.

Claim 26

A switching method as claimed in claim 18, further comprising the step of comparing first cell count with a threshold value and disabling the step (d) when said first cell count is smaller than said threshold value.

Claim 27

A switching method for an asynchronous transfer mode (ATM) switching system, comprising the steps of: a) producing a timing cell; b) multiplexing sad timing cell with ATM cells to produce a multiplexed ATM call stream; c) storing the multiplexed ATM cell stream in first and second store-and-forward buffers and forwarding the multiplexed ATM cell stream from each of the first and second store-and-forward buffers; d) detecting said timing cell multiplexed in said ATM cell stream and producing a first call count and a second call count representative of numbers of cells stored in the first and second store-and-forward buffers, respectively; e) detecting a difference between said first and second cell counts; f) controlling said second store-and-forward buffer in accordance with said difference so that the count of cells in said second store-and-forward buffer approaches the count of cells in the first store-and-forward buffer; and g) normally coupling the ATM cell stream forwarded from said first store-and-forward buffer to an output port of said ATM switching system and coupling the ATM cell stream forwarded from said second store-and-forward buffer, instead of from the first store-and-forward buffer, to said output port in reponse to a command signal.

Claim 28

A switching method for an asynchronous transfer mode (ATM) switching system, comprising the steps of: a) producing a timing cell; b) multiplexing sad timing cell with ATM cells to produce a multiplexed ATM call stream; c) storing the multiplexed ATM cell stream in first and second store-and-forward buffers and forwarding the multiplexed ATM cell stream from each of the first and second store-and-forward buffers; d) detecting said timing cell multiplexed in said ATM cell stream and producing a first call count and a second call count representative of numbers of cells stored in the first and second store-and-forward buffers, respectively; e) detecting a difference between said first and second cell counts; f) controlling said second store-and-forward buffer in accordance with said difference so that the count of cells in said second store-and-forward buffer approaches the count of cells in the first store-and-forward buffer; and g) normally coupling the ATM cell stream forwarded from said first store-and-forward buffer to an output port of said ATM switching system and coupling the ATM cell stream forwarded from said second store-and-forward buffer, instead of from the first store-and-forward buffer, to said output port in reponse to a command signal.

Claim 29

A switching method as claimed in claim 20, wherein the step (g) comprises the steps of detecting said timing cell forwarded from one of said buffers and coupling the ATM cell stream forwarded from said second store-and-forward buffer to said output port at said instant the timing cell from one of the buffers is detected.