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US5670398A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing thin film transistor having a double channel

Assignee: SK Hynix Inc
•
Filing: 1995-11-20
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Granted: 1997-09-23
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Expires: 2015-11-20
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Abstract

Abstract This invention provides a method for manufacturing a thin film transistor which comprised the steps of providing an oxide layer; etching a portion of the oxide layer so that a recess is formed; forming a first channel layer on the resulting structure; forming a first gate oxide layer on the first channel layer in a portion including the recess region; forming a polysilicon layer on the resulting structure, filling in the recess region; etching back the polysilicon layer until the surface of a portion of the first gate oxide layer, leaving the residual layer on the first channel layer, which is exposed by the first gate oxide layer, wherein the surface of the resulting structure has uniform topology by the etching process; forming a second gate oxide layer on the polysilicon layer; forming a second channel layer on the resulting structure; and implanting impurity ions for forming source/drain regions, whereby the source/drain region consists of multi-layers, the first channel layer, the second polysilicon layer and the second channel layer.

Inventors

  • 👤 Sung Wook Yin
  • 👤 Yun Ki Kim

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 18:40
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/60; H10D30/67; H10D30/674; H10D30/6757; H10D30/0312

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 171 words
A method for manufacturing a thin film transistor having double channels comprising the steps of: providing an oxide layer; etching a portion of the oxide layer so that a recess is formed; forming a first channel layer on the resulting structure; forming a first gate oxide layer on the first channel layer in a portion including the recess region; forming a polysilicon layer on the resulting structure, filling in the recess region; etching back the polysilicon layer until the surface of a portion of the first gate oxide layer, leaving the residual layer on the first channel layer, which is exposed by the first gate oxide layer, wherein the surface of the resulting structure has uniform topology by the etching process; forming a second gate oxide layer on the polysilicon layer; forming a second channel layer on the resulting structure; and implanting impurity ions for forming source/drain regions, whereby the source/drain region consists of multi-layers, which consists of the first channel layer, the second polysilicon layer and the second channel layer.
Claim 2
Independent Claim 171 words
A method for manufacturing a thin film transistor having double channels comprising the steps of: providing an oxide layer; etching a portion of the oxide layer so that a recess is formed; forming a first channel layer on the resulting structure; forming a first gate oxide layer on the first channel layer in a portion including the recess region; forming a polysilicon layer on the resulting structure, filling in the recess region; etching back the polysilicon layer until the surface of a portion of the first gate oxide layer, leaving the residual layer on the first channel layer, which is exposed by the first gate oxide layer, wherein the surface of the resulting structure has uniform topology by the etching process; forming a second gate oxide layer on the polysilicon layer; forming a second channel layer on the resulting structure; and implanting impurity ions for forming source/drain regions, whereby the source/drain region consists of multi-layers, which consists of the first channel layer, the second polysilicon layer and the second channel layer.
Claim 3
Dependent Claim 16 words
A method according to claim 1, wherein the first and second channel layer are polysilicon layers.

References Cited (Backward Citations)

US5298782A Cited
US5372959A Cited
US5348899A Cited
US5362669A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-09-22 2001-03-24 2001-09-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-09-22 2005-03-24 2005-09-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-09-22 2009-03-24 2009-09-23 $7700.00 Window Closed / Lapsed

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