US5668759A
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Method for erasing and verifying nonvolatile semiconductor memory
Assignee: NEC Corp
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Filing: 1995-04-11
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Granted: 1997-09-16
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Expires: 2015-04-11
Abstract
Abstract In a nonvolatile semiconductor memory device including memory cells, a predetermined number of the memory cells are simultaneously erased. Only when at least one of the memory cells is overerased, i.e., is in a depletion state, a threshold voltage recovering operation is performed upon all of the memory cells, to relieve the overerased memory cell and suppress the deviation of threshold voltage.
Inventors
- 👤 Tetsuya Ohtsuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:02
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3409; G11C16/08; G11C16/10; G11C16/14; G11C16/16; G11C16/3436; G11C16/344; G11C16/3445
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
220 words
A method for erasing and verifying a nonvolatile semiconductor memory device including nonvolatile memory cells, comprising the steps of: a) performing a write operation upon a certain number of said nonvolatile memory cells; b) determining whether or not said write operation is carried out normally; c) performing a flash erase operation upon said certain number of said nonvolatile memory cells after said write operation is carried out normally; d) determining whether or not said flash erase operation is carried out normally; e) determining whether or not at least one of said certain number of said nonvolatile memory cells is in a depletion state after said flash erase operation is carried out normally; f) performing a threshold voltage recovering operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter an enhancement state only after at least one of said certain number of said nonvolatile memory cells is determined to be in a depletion state; g) determining whether or not said certain number of said nonvolatile memory cells are in an erase completion state after said threshold voltage recovering operation is carried out; and h) determining said nonvolatile semiconductor memory device as a defective device when at least one of said nonvolatile memory cells is in a non-erase completion state.
Claim 2
Independent Claim
220 words
A method for erasing and verifying a nonvolatile semiconductor memory device including nonvolatile memory cells, comprising the steps of: a) performing a write operation upon a certain number of said nonvolatile memory cells; b) determining whether or not said write operation is carried out normally; c) performing a flash erase operation upon said certain number of said nonvolatile memory cells after said write operation is carried out normally; d) determining whether or not said flash erase operation is carried out normally; e) determining whether or not at least one of said certain number of said nonvolatile memory cells is in a depletion state after said flash erase operation is carried out normally; f) performing a threshold voltage recovering operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter an enhancement state only after at least one of said certain number of said nonvolatile memory cells is determined to be in a depletion state; g) determining whether or not said certain number of said nonvolatile memory cells are in an erase completion state after said threshold voltage recovering operation is carried out; and h) determining said nonvolatile semiconductor memory device as a defective device when at least one of said nonvolatile memory cells is in a non-erase completion state.
Claim 3
Dependent Claim
79 words
A method as set forth in claim 1, further comprising the steps of: i) performing a flash erase operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter a depletion state after at least one of said certain number of said nonvolatile memory cells is determined to be in a depletion state; and j) repeating said steps f) to h) after said step i) is carried out.
Claim 4
Dependent Claim
25 words
A method as set forth in claim 2, further comprising a step of repeating said steps i) and j) within a definite number of times.
Claim 5
Dependent Claim
27 words
A method as set forth in claim 1, further comprising a step of k) repeating said step a) after said write operation is not carried out normally.
Claim 6
Dependent Claim
23 words
A method as set forth in claim 4, further comprising a step of repeating said step k) within a definite number of times.
Claim 7
Dependent Claim
28 words
A method as set forth in claim 1, further comprising a step of l) repeating said step c) after said flash erase operation is not carried out normally.
Claim 8
Dependent Claim
23 words
A method as set forth in claim 6, further comprising a step of repeating said step l) within a definite number of times.
Claim 9
Independent Claim
262 words
A method for erasing and verifying a nonvolatile semiconductor memory device including nonvolatile memory cells, comprising the steps of: a) performing a write operation upon a certain number of said nonvolatile memory cells; b) determining whether or not said write operation is carried out normally; c) performing a flash erase operation upon said certain number of said nonvolatile memory cells after said write operation is carried out normally; d) determining whether or not said flash erase operation is carried out normally; e) determining whether or not at least one of said certain number of said nonvolatile memory cells is in a depletion state after said flash erase operation is carried out normally; f) performing a flash erase operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter a depletion state only after at least one of said certain number of said nonvolatile memory cells is determined to be in a depletion state; and g) performing a threshold voltage recovering operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter an enhancement state after said flash erase operation in step f) is carried out; h) determining whether or not said certain number of said nonvolatile memory cells are in an erase completion state after said threshold voltage recovering operation is carried out; and i) determining said nonvolatile semiconductor memory device as a defective device when at least one of said nonvolatile memory cells is in a non-erase completion state.
Claim 10
Independent Claim
262 words
A method for erasing and verifying a nonvolatile semiconductor memory device including nonvolatile memory cells, comprising the steps of: a) performing a write operation upon a certain number of said nonvolatile memory cells; b) determining whether or not said write operation is carried out normally; c) performing a flash erase operation upon said certain number of said nonvolatile memory cells after said write operation is carried out normally; d) determining whether or not said flash erase operation is carried out normally; e) determining whether or not at least one of said certain number of said nonvolatile memory cells is in a depletion state after said flash erase operation is carried out normally; f) performing a flash erase operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter a depletion state only after at least one of said certain number of said nonvolatile memory cells is determined to be in a depletion state; and g) performing a threshold voltage recovering operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter an enhancement state after said flash erase operation in step f) is carried out; h) determining whether or not said certain number of said nonvolatile memory cells are in an erase completion state after said threshold voltage recovering operation is carried out; and i) determining said nonvolatile semiconductor memory device as a defective device when at least one of said nonvolatile memory cells is in a non-erase completion state.
Claim 11
Dependent Claim
33 words
A method as set forth in claim 8, further comprising a step of j) repeating said steps d) to i) after said nonvolatile semiconductor memory device is determined to be a defective device.
Claim 12
Dependent Claim
23 words
A method as set forth in claim 9, further comprising a step of repeating said step l) within a definite number of times.
Claim 13
Dependent Claim
27 words
A method as set forth in claim 8, further comprising a step of m) repeating said step a) after said write operation is not carried out normally.
Claim 14
Dependent Claim
23 words
A method as set forth in claim 11, further comprising a step of repeating said step m) within a definite number of times.
Claim 15
Dependent Claim
28 words
A method as set forth in claim 8, further comprising a step of n) repeating said step c) after said flash erase operation is not carried out normally.
Claim 16
Dependent Claim
23 words
A method as set forth in claim 13, further comprising a step of repeating said step n) within a definite number of times.
Claim 17
Independent Claim
186 words
A method for erasing and verifying a nonvolatile semiconductor memory device including nonvolatile memory cells, comprising the steps of: a) performing a flash erase operation upon a certain number of said nonvolatile memory cells; b) determining whether or not said flash erase operation is carried out normally; c) determining whether or not at least one of said certain number of said nonvolatile memory cells is in a depletion state after said flash erase operation is carried out normally; d) performing a threshold voltage recovering operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter an enhancement state only after at least one of said certain number of said nonvolatile memory cells is determined to be in a depletion state; e) determining whether or not said certain number of said nonvolatile memory cells are in an erase completion state after said threshold voltage recovering operation is carried out; and f) determining said nonvolatile semiconductor memory device as a defective device when at least one of said nonvolatile memory cells is in a non-erase depletion state.
Claim 18
Independent Claim
186 words
A method for erasing and verifying a nonvolatile semiconductor memory device including nonvolatile memory cells, comprising the steps of: a) performing a flash erase operation upon a certain number of said nonvolatile memory cells; b) determining whether or not said flash erase operation is carried out normally; c) determining whether or not at least one of said certain number of said nonvolatile memory cells is in a depletion state after said flash erase operation is carried out normally; d) performing a threshold voltage recovering operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter an enhancement state only after at least one of said certain number of said nonvolatile memory cells is determined to be in a depletion state; e) determining whether or not said certain number of said nonvolatile memory cells are in an erase completion state after said threshold voltage recovering operation is carried out; and f) determining said nonvolatile semiconductor memory device as a defective device when at least one of said nonvolatile memory cells is in a non-erase depletion state.
Claim 19
Dependent Claim
79 words
A method as set forth in claim 15, further comprising the steps of: g) performing a flash erase operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter a depletion state after at least one of said certain number of said nonvolatile memory cells is determined to be in a depletion state; and h) repeating said steps d) to f) after said step g) is carried out.
Claim 20
Dependent Claim
25 words
A method as set forth in claim 16, further comprising a step of repeating said steps g) and h) within a definite number of times.
Claim 21
Dependent Claim
27 words
A method as set forth in claim 15, further comprising a step of i) repeating said step a) after said write operation is not carried out normally.
Claim 22
Dependent Claim
23 words
A method as set forth in claim 18, further comprising a step of repeating said step i) within a definite number of times.
Claim 23
Independent Claim
228 words
A method for erasing and verifying a nonvolatile semiconductor memory device including nonvolatile memory cells, comprising the steps of: a) performing a flash erase operation upon a certain number of said nonvolatile memory cells; b) determining whether or not said flash erase operation is carried out normally; c) determining whether or not at least one of said certain number of said nonvolatile memory cells is in a depletion state after said flash erase operation is carried out normally; d) performing a flash erase operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter a depletion state only after at least one of said certain number of said nonvolatile memory cells is determined to be in a depletion state; and e) performing a threshold voltage recovering operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter an enhancement state after said flash erase operation in step d) is carried out; f) determining whether or not said certain number of said nonvolatile memory cells are in an erase depletion state after said threshold voltage recovering operation is carried out; and g) determining said nonvolatile semiconductor memory device as a defective device when at least one of said nonvolatile memory cells is in a non-erase completion state.
Claim 24
Independent Claim
228 words
A method for erasing and verifying a nonvolatile semiconductor memory device including nonvolatile memory cells, comprising the steps of: a) performing a flash erase operation upon a certain number of said nonvolatile memory cells; b) determining whether or not said flash erase operation is carried out normally; c) determining whether or not at least one of said certain number of said nonvolatile memory cells is in a depletion state after said flash erase operation is carried out normally; d) performing a flash erase operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter a depletion state only after at least one of said certain number of said nonvolatile memory cells is determined to be in a depletion state; and e) performing a threshold voltage recovering operation upon said certain number of said nonvolatile memory cells until all of said certain number of said nonvolatile memory cells enter an enhancement state after said flash erase operation in step d) is carried out; f) determining whether or not said certain number of said nonvolatile memory cells are in an erase depletion state after said threshold voltage recovering operation is carried out; and g) determining said nonvolatile semiconductor memory device as a defective device when at least one of said nonvolatile memory cells is in a non-erase completion state.
Claim 25
Dependent Claim
31 words
A method as set forth in claim 20, further comprising a step of h) repeating said steps d) to after said nonvolatile semiconductor memory device determined to be a defective device.
Claim 26
Dependent Claim
23 words
A method as set forth in claim 21, further comprising a step of repeating said step h) within a definite number of times.
Claim 27
Dependent Claim
28 words
A method as set forth in claim 20, further comprising a step of i) repeating said step a) after said flash erase operation is not carried out normally.
Claim 28
Dependent Claim
23 words
A method as set forth in claim 23, further comprising a step of repeating said step i) within a definite number of times.
Claim 29
Independent Claim
306 words
A method for erasing and verifying a nonvolatile semiconductor memory device including nonvolatile memory cells, comprising the steps of: a) performing a write operation upon a certain number of said nonvolatile memory cells; b) determining whether or not a threshold voltage of each of said certain number of said nonvolatile memory cells is higher than a first reference voltage after said write operation is carried out; c) performing a flash erase operation upon said certain number of said nonvolatile memory cells when all threshold voltages of said certain number of said nonvolatile memory cells are higher than said first reference voltage; d) determining whether or not threshold voltages of said certain number of said nonvolatile memory cells are lower than a second reference voltage after said flash erase operation is carried out; e) determining whether or not a threshold voltage of each of said nonvolatile memory cells is higher than a third reference voltage when all threshold voltages of said certain number of said nonvolatile memory cells are higher than said second reference voltage; f) performing a threshold voltage recovering operation upon said certain number of said nonvolatile memory cells until threshold voltages of all of said certain number of said nonvolatile memory cells become higher than said third reference voltage, when at least one of said certain number of said nonvolatile memory cells is determined to be not higher than said third reference voltage; g) determining whether or not a threshold voltage of each of said certain number of said nonvolatile memory cells is lower than said second reference voltage after said threshold voltage recovering operation is carried out; and h) determining said nonvolatile semiconductor memory device as a defective device when a threshold voltage of at least one of said nonvolatile memory cells is determined to be not lower than said second reference voltage.
Claim 30
Independent Claim
306 words
A method for erasing and verifying a nonvolatile semiconductor memory device including nonvolatile memory cells, comprising the steps of: a) performing a write operation upon a certain number of said nonvolatile memory cells; b) determining whether or not a threshold voltage of each of said certain number of said nonvolatile memory cells is higher than a first reference voltage after said write operation is carried out; c) performing a flash erase operation upon said certain number of said nonvolatile memory cells when all threshold voltages of said certain number of said nonvolatile memory cells are higher than said first reference voltage; d) determining whether or not threshold voltages of said certain number of said nonvolatile memory cells are lower than a second reference voltage after said flash erase operation is carried out; e) determining whether or not a threshold voltage of each of said nonvolatile memory cells is higher than a third reference voltage when all threshold voltages of said certain number of said nonvolatile memory cells are higher than said second reference voltage; f) performing a threshold voltage recovering operation upon said certain number of said nonvolatile memory cells until threshold voltages of all of said certain number of said nonvolatile memory cells become higher than said third reference voltage, when at least one of said certain number of said nonvolatile memory cells is determined to be not higher than said third reference voltage; g) determining whether or not a threshold voltage of each of said certain number of said nonvolatile memory cells is lower than said second reference voltage after said threshold voltage recovering operation is carried out; and h) determining said nonvolatile semiconductor memory device as a defective device when a threshold voltage of at least one of said nonvolatile memory cells is determined to be not lower than said second reference voltage.
Claim 31
Dependent Claim
91 words
A method as set forth in claim 25, further comprising the steps of: i) performing a flash erase operation upon said certain number of said nonvolatile memory cells until all threshold voltages of said certain number of said nonvolatile memory cells become lower than said second reference voltage when a threshold voltage of at least one of said certain number of said nonvolatile memory cells is determined to be not higher than said third reference voltage; and j) repeating said steps f) to h) after said step i) is carried out.
Claim 32
Dependent Claim
25 words
A method as set forth in claim 26, further comprising a step of repeating said steps i) and j) within a definite number of times.
Claim 33
Dependent Claim
43 words
A method as set forth in claim 25, further comprising a step of k) repeating said step a) when a threshold voltage of at least one of said certain number of said nonvolatile memory cells is not higher than said first reference voltage.
Claim 34
Dependent Claim
23 words
A method as set forth in claim 28, further comprising a step of repeating said step k) within a definite number of times.
Claim 35
Dependent Claim
43 words
A method as set forth in claim 25, further comprising a step of l) repeating said step c) when a threshold voltage of at least one of said certain number of said nonvolatile memory cell is not lower than said second reference voltage.
Claim 36
Dependent Claim
23 words
A method as set forth in claim 30, further comprising a step of repeating said step l) within a definite number of times.
Claim 37
Independent Claim
291 words
A method for erasing and verifying a nonvolatile semiconductor memory device including nonvolatile memory cells, comprising the steps of: a) performing a flash erase operation upon a certain number of said nonvolatile memory cells; b) determining whether or not a threshold voltage of said certain number of said nonvolatile memory cells is lower than a second reference voltage after said flash erase operation is carried out; c) determining whether or not a threshold voltage of each of said nonvolatile memory cells is lower than a third reference voltage when all of threshold voltages of said certain number of said nonvolatile memory cells are lower than said second reference voltage; d) performing a flash erase operation upon said certain number of said nonvolatile memory cells, until all threshold voltages of said certain number of said nonvolatile memory cells becomes lower than said second reference voltage when a threshold voltage of at least one of said certain number of said nonvolatile memory cells is determined to be lower than said third reference voltage; and e) performing a threshold voltage recovering operation upon said certain number of said nonvolatile memory cells until threshold voltages of all of said certain number of said nonvolatile memory cells become higher than said third reference voltage, after said flash erase operation in step d) is carried out; f) determining whether or not a threshold voltage of each of said certain number of said nonvolatile memory cells is lower than said second reference voltage after said threshold voltage recovering operation is carried out; and g) determining said nonvolatile semiconductor memory device as a defective device when a threshold voltage of at least one of said nonvolatile memory cells is determined to be not lower than said second reference voltage.
Claim 38
Independent Claim
291 words
A method for erasing and verifying a nonvolatile semiconductor memory device including nonvolatile memory cells, comprising the steps of: a) performing a flash erase operation upon a certain number of said nonvolatile memory cells; b) determining whether or not a threshold voltage of said certain number of said nonvolatile memory cells is lower than a second reference voltage after said flash erase operation is carried out; c) determining whether or not a threshold voltage of each of said nonvolatile memory cells is lower than a third reference voltage when all of threshold voltages of said certain number of said nonvolatile memory cells are lower than said second reference voltage; d) performing a flash erase operation upon said certain number of said nonvolatile memory cells, until all threshold voltages of said certain number of said nonvolatile memory cells becomes lower than said second reference voltage when a threshold voltage of at least one of said certain number of said nonvolatile memory cells is determined to be lower than said third reference voltage; and e) performing a threshold voltage recovering operation upon said certain number of said nonvolatile memory cells until threshold voltages of all of said certain number of said nonvolatile memory cells become higher than said third reference voltage, after said flash erase operation in step d) is carried out; f) determining whether or not a threshold voltage of each of said certain number of said nonvolatile memory cells is lower than said second reference voltage after said threshold voltage recovering operation is carried out; and g) determining said nonvolatile semiconductor memory device as a defective device when a threshold voltage of at least one of said nonvolatile memory cells is determined to be not lower than said second reference voltage.
Claim 39
Dependent Claim
33 words
A method as set forth in claim 32, further comprising a step of h) repeating said steps d) to g) after said nonvolatile semiconductor memory device determined to be a defective device is.
Claim 40
Dependent Claim
23 words
A method as set forth in claim 33, further comprising a step of repeating said step h) within a definite number of times.
Claim 41
Dependent Claim
43 words
A method as set forth in claim 32, further comprising a step of i) repeating said step c) when a threshold voltage of at least one of said certain number of said nonvolatile memory cell is not lower than said second reference voltage.
Claim 42
Dependent Claim
23 words
A method as set forth in claim 35, further comprising a step of repeating said step i) within a definite number of times.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-15 | 2001-03-17 | 2001-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-15 | 2005-03-17 | 2005-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-15 | 2009-03-17 | 2009-09-16 | $7700.00 | Window Closed / Lapsed |