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US5668602A Expired / Lapsed US ⏱️ 0.0 years remaining

Real-time television image pixel multiplication methods and apparatus

Assignee: Individual
•
Filing: 1995-08-09
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Granted: 1997-09-16
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Expires: 2015-08-09
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Abstract

Abstract Circuitry and methods multiply the number of pixels in a television image without the need for changes in current transmission standards. One memory array or storage buffer is used to store one image, while data is being read from another memory or array storage buffer. The role of the two memory arrays changes with every incoming image, the memory array that was in the read mode is switched to the write mode, and vice-versa. The image read is interpolated through pixel replication in two-dimensions, followed by a square symmetrical two-dimensional low-pass filter, which provides interpolation based on the Sampling Theorem. This may be a two-dimensional (2-D) circularly-symmetrical high-pass filter for image enhancement. Interpolation may alternatively be carried out through a one-dimensional (1-D) filter, or through the Discrete Cosine transform. A description of a circuit realizing a 2-D infinite impulse response filter and the filter coefficients for a square symmetrical low-pass filter having near-linear phase is provided. Circuits for addressing the two memory arrays are also described for displaying video images through either progressive or interlaced scanning.

Inventors

  • 👤 Maher Ahmed Sid-Ahmed

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-10 00:59
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/01; H04N7/0102; H04N7/0117; H04N7/012; H04N7/0125; H04N7/12

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 73 words
A method of expanding the number of pixels used to display a video image, comprising the steps of: receiving pixels associated with an incoming digitized video image; replicating each pixel; low-pass filtering the replicated pixels in two dimensions using a square symmetrical filter to provide interpolated values; converting the interpolated values into analog form; and displaying the converted pixels at the same frame rate as that associated with the incoming digitized video image.
Claim 2
Independent Claim 73 words
A method of expanding the number of pixels used to display a video image, comprising the steps of: receiving pixels associated with an incoming digitized video image; replicating each pixel; low-pass filtering the replicated pixels in two dimensions using a square symmetrical filter to provide interpolated values; converting the interpolated values into analog form; and displaying the converted pixels at the same frame rate as that associated with the incoming digitized video image.
Claim 3
Dependent Claim 19 words
The method of claim 1, further including the step of high-pass filtering the low-pass-filtered pixels to enhance their sharpness.
Claim 4
Independent Claim 133 words
A system for multiplying the number of pixels associated with a digitized video image, comprising: a source of a digitized video image having alternating fields; two read/write memories in communication with a common output bus; write-mode circuitry operative to enable the memories so that each is written with data representative of an alternating field of the image; read-mode circuitry operative to output the data onto the common bus, the read-mode circuitry operating at a frequency higher than that at which the pixels were written to memory, thereby expanding the number of pixels along each row and between consecutive rows; low-pass filtering means operative to filter the expanded pixels symmetrically in two dimensions to produce interpolated values; and a digital-to-analog converter to convert the digitally filtered, interpolated values into analog form for subsequent display.
Claim 5
Independent Claim 133 words
A system for multiplying the number of pixels associated with a digitized video image, comprising: a source of a digitized video image having alternating fields; two read/write memories in communication with a common output bus; write-mode circuitry operative to enable the memories so that each is written with data representative of an alternating field of the image; read-mode circuitry operative to output the data onto the common bus, the read-mode circuitry operating at a frequency higher than that at which the pixels were written to memory, thereby expanding the number of pixels along each row and between consecutive rows; low-pass filtering means operative to filter the expanded pixels symmetrically in two dimensions to produce interpolated values; and a digital-to-analog converter to convert the digitally filtered, interpolated values into analog form for subsequent display.
Claim 6
Dependent Claim 15 words
The system of claim 3 wherein the digital filtering means includes a square-response-type low-pass filter.
Claim 7
Dependent Claim 14 words
The system of claim 3 wherein the digital filtering means includes two one-dimensional filters.
Claim 8
Dependent Claim 78 words
The system of claim 3 further including: a second pair of read/write memories in communication with a second common output bus, each memory having a capacity sufficient to store data representative of the expanded pixels associated with both fields of the image; and read-mode circuitry operative to address the second pair of read/write memories so that while one of the memories is being written, the other may be read out to the digital-to-analog converter over the second bus.
Claim 9
Dependent Claim 20 words
The system of claim 6 wherein the read/write memory being read out is done so on a progressive scan basis.
Claim 10
Dependent Claim 20 words
The system of claim 6 wherein the read/write memory being read out is done so on an interlaced scan basis.

References Cited (Backward Citations)

US4322750A Cited
US4364090A Cited
US4282546A Cited
US4435728A Cited
US4603351A Cited
US4706113A Cited
US4868656A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-09-15 2001-03-17 2001-09-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-09-15 2005-03-17 2005-09-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-09-15 2009-03-17 2009-09-16 $7700.00 Window Closed / Lapsed

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