US5668549A
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Radix 2 architecture and calibration technique for pipelined analog to digital converters
Assignee: National Semiconductor Corp
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Filing: 1994-11-10
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Granted: 1997-09-16
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Expires: 2014-11-10
Abstract
Abstract In a pipelined radix 2 analog to digital converter, a method of analog residue formation uses an overflow reduction stage which takes an analog input and outputs a digital value of +2, 0, or -2 and an analog residue which is twice the analog input minus the digital output value times a reference voltage. A calibration technique allows a pipelined analog to digital converter using the overflow reduction stages to produce a corrected output requiring one addition per pipeline stage. The residue portion of the overflow reduction stage can be constructed using an operational amplifier, two capacitors, one of which has twice the capacitance of the other, and three on-off type switches. A radix 2 pipelined converter is constructed using a combination of standard 1-bit stages and overflow reduction stages. The analog residue is passed from stage to stage as an amplifier remainder as the digital codes are extracted in a pipelined analog to digital converter. The overflow reduction stage reduces out-of-range residues back to in-range residues. Using three digital output values where the difference between any two is greater than one raw output code prevents the possibility of multiple representations of the same code and thus allows for the prevention of non-monotonic input-output transfer functions. The self-calibration and raw output code correction schemes prevent non-monotonicities and missing codes in the input-output transfer functions.
Inventors
- 👤 Ion E. Opris
- 👤 Laurence D. Lewicki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:21
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0675; H03M1/069; H03M1/10; H03M1/1009; H03M1/1033; H03M1/1057; H03M1/12; H03M1/34; H03M1/38; H03M1/44
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
156 words
A method for correcting raw digital output of an analog to digital converter having a plurality of single bit stages with two digital output states and at least one overflow reduction stage having three digital output states to produce a corrected output, the method comprising the steps of: for each single bit stage, selectively either adding or not adding to the raw digital output one digital correction quantity which corresponds to that stage from a set of predetermined digital correction quantities, wherein the selective adding or not adding depends upon the digital output state of that stage; and for each overflow reduction stage, selectively adding or not adding to the raw digital output one of two digital correction quantities which correspond to two of the output states of that stage from a set of predetermined digital correction quantities, wherein the selective adding or not adding depends upon the digital output state of that overflow reduction stage.
Claim 2
Independent Claim
156 words
A method for correcting raw digital output of an analog to digital converter having a plurality of single bit stages with two digital output states and at least one overflow reduction stage having three digital output states to produce a corrected output, the method comprising the steps of: for each single bit stage, selectively either adding or not adding to the raw digital output one digital correction quantity which corresponds to that stage from a set of predetermined digital correction quantities, wherein the selective adding or not adding depends upon the digital output state of that stage; and for each overflow reduction stage, selectively adding or not adding to the raw digital output one of two digital correction quantities which correspond to two of the output states of that stage from a set of predetermined digital correction quantities, wherein the selective adding or not adding depends upon the digital output state of that overflow reduction stage.
Claim 3
Dependent Claim
44 words
A method for correcting raw digital output of an analog to digital converter as in claim 1, wherein the selected adding or not adding step corresponding to each stage is performed prior to the production of the digital output state for the subsequent stage.
Claim 4
Independent Claim
310 words
An apparatus for performing a multi-stage pipelined analog to digital conversion comprising: at least one overflow reduction stage, each stage having a first digital output, a first analog input, and a first analog residue output, and each stage including, means for outputting the first digital output as a first logic value and a first analog residue which is substantially twice the sum of the first analog input plus a first predetermined reference level when the analog input is less than negative one half times the first predetermined reference level, means for outputting the first digital output as a second logic value and the first analog residue which is substantially twice the first analog input when the first analog input is between negative one half times the first predetermined reference level and positive one half times the first predetermined reference level, and means for outputting the first digital output as a third logic value and the first analog residue which is substantially twice the sum of the first analog input minus the first predetermined reference voltage when the first analog input is greater than positive one half times the first predetermined reference level; and at least one single-bit stage, each stage having a second digital output, a second analog input, and a second analog residue output, and each stage including, means for outputting the second digital output as a first logic value and a second analog residue which is substantially the first predetermined reference voltage plus twice the second analog input when the analog input is less than a second predetermined reference level, and means for outputting the second digital output as a second logic value and the second analog residue which is substantially sum of the negative of the first predetermined reference voltage plus twice the analog input when the analog input is greater than the second predetermined reference level.
Claim 5
Independent Claim
310 words
An apparatus for performing a multi-stage pipelined analog to digital conversion comprising: at least one overflow reduction stage, each stage having a first digital output, a first analog input, and a first analog residue output, and each stage including, means for outputting the first digital output as a first logic value and a first analog residue which is substantially twice the sum of the first analog input plus a first predetermined reference level when the analog input is less than negative one half times the first predetermined reference level, means for outputting the first digital output as a second logic value and the first analog residue which is substantially twice the first analog input when the first analog input is between negative one half times the first predetermined reference level and positive one half times the first predetermined reference level, and means for outputting the first digital output as a third logic value and the first analog residue which is substantially twice the sum of the first analog input minus the first predetermined reference voltage when the first analog input is greater than positive one half times the first predetermined reference level; and at least one single-bit stage, each stage having a second digital output, a second analog input, and a second analog residue output, and each stage including, means for outputting the second digital output as a first logic value and a second analog residue which is substantially the first predetermined reference voltage plus twice the second analog input when the analog input is less than a second predetermined reference level, and means for outputting the second digital output as a second logic value and the second analog residue which is substantially sum of the negative of the first predetermined reference voltage plus twice the analog input when the analog input is greater than the second predetermined reference level.
Claim 6
Dependent Claim
30 words
An apparatus as in claim 3, wherein the apparatus is 1-bit, 11-stage, and the fourth and the eighth stages are overflow reduction stages, and all other stages are single-bit stages.
Claim 7
Dependent Claim
35 words
An apparatus as in claim 3, wherein a plurality of overflow reduction stages and a plurality of single bit stages are connected in a pipeline such that no two overflow reduction stages are directly cascaded.
Claim 8
Dependent Claim
43 words
An apparatus as in claim 3, wherein the apparatus is configured in an recirculating algorithmic implementation, such that one or more single bit stages are followed by one overflow reduction stage, and the first analog output is fedback to the second analog input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-15 | 2001-03-17 | 2001-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-15 | 2005-03-17 | 2005-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-15 | 2009-03-17 | 2009-09-16 | $7700.00 | Window Closed / Lapsed |