US5668489A
Expired / Lapsed
US
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Dead-time generating circuit
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-01-02
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Granted: 1997-09-16
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Expires: 2016-01-02
Abstract
Abstract A dead-time generating circuit includes a first gate for generating a gate signal corresponding to a predetermined cutting width, and a second gate for cutting an input signal to be cut by the gate signal by the predetermined cutting width determined by a user and outputting the result. Therefore, an arbitrary block of a pulse width modulated (PWM) signal (whatever it may be in a logic "high" or "low") applied to the inverter of an AC servo driving circuit can be cut constantly by a predetermined cutting width. Also, the cutting width can be adjusted easily by the user.
Inventors
- 👤 Sang-Hyun Jin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:40
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
90 words
A circuit for stopping a normal response to an input signal by cutting-off said input signal for a predetermined time interval, said circuit comprising: a first gate means for generating a gate signal corresponding to said predetermined time interval determined by a user in response to said input signal and a control signal corresponding to said predetermined time interval; and a second gate means coupled to said input signal for cutting off said input signal by said predetermined time interval in response to said gate signal and outputting the result.
Claim 2
Dependent Claim
90 words
A circuit for stopping a normal response to an input signal by cutting-off said input signal for a predetermined time interval, said circuit comprising: a first gate means for generating a gate signal corresponding to said predetermined time interval determined by a user in response to said input signal and a control signal corresponding to said predetermined time interval; and a second gate means coupled to said input signal for cutting off said input signal by said predetermined time interval in response to said gate signal and outputting the result.
Claim 3
Dependent Claim
35 words
A dead-time generating circuit as claimed in claim 1, wherein said second gate means cuts the forehead of the logic "high" portion of said input signal by said predetermined time interval and outputs the result.
Claim 4
Dependent Claim
166 words
A dead-time generating circuit comprising: a first D-flipflop for receiving an input signal to be cut by a predetermined time interval at a clock port, receiving a logic "high" state at a preset port and a D-input port, and applying a first gate signal to a clear port, to output a second gate signal; an up/down counter for starting counting operation by the second gate signal, down-counting counted input values loaded to N data input ports by a predetermined clock signal to output counted output values, and outputting said first gate signal generated when the counted output values are 0; a means for discretionarily adjusting said counted input values corresponding to said time interval; and a second D-flipflop for receiving said first gate signal at a clock port, and receiving a logic "high" state at a D-input port and a clear port, and receiving a logic "high" state at a preset port, to output a signal obtained by cutting-off the input signal by said time interval.
Claim 5
Dependent Claim
166 words
A dead-time generating circuit comprising: a first D-flipflop for receiving an input signal to be cut by a predetermined time interval at a clock port, receiving a logic "high" state at a preset port and a D-input port, and applying a first gate signal to a clear port, to output a second gate signal; an up/down counter for starting counting operation by the second gate signal, down-counting counted input values loaded to N data input ports by a predetermined clock signal to output counted output values, and outputting said first gate signal generated when the counted output values are 0; a means for discretionarily adjusting said counted input values corresponding to said time interval; and a second D-flipflop for receiving said first gate signal at a clock port, and receiving a logic "high" state at a D-input port and a clear port, and receiving a logic "high" state at a preset port, to output a signal obtained by cutting-off the input signal by said time interval.
Claim 6
Dependent Claim
34 words
A dead-time generating circuit as claimed in claim 3, wherein said second D-flipflop cuts the forehead of the logic "high" portion of said input signal by said predetermined time interval and output the results.
References Cited (Backward Citations)
US5003194A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-15 | 2001-03-17 | 2001-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-15 | 2005-03-17 | 2005-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-15 | 2009-03-17 | 2009-09-16 | $7700.00 | Window Closed / Lapsed |