High frequency analog transistors, method of fabrication and circuit implementation

Claim 2

An integrated circuit along a semiconductor surface comprising at least one NPN and one PNP bipolar transistors, each of said transistors having a collector having a more heavily doped layer therein, a base and an emitter with a polycrystalline silicon contact, where: (a) the thickness of each base and the contiguous emitter and the doping profiles thereof cooperating to provide an Early Voltage of Ea for each of said transistors, (i) the barrier provided by the polycrystalline silicon emitter contact and (ii) the thickness and doping profile of the emitter and the contiguous base cooperating to provide an emitter injection efficiency sufficient to produce a current gain of β for each of said transistors, the product of Ea and β for each of said transistors being not less than about 800 volts; (b) (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage of not less than about 12 volts for each of said transistors; and (c) (i) the thickness of the base and the doping profile thereof, (ii) the geometry and doping profile of the base underlying the contiguous emitter and (iii) the resistance of the base between the contiguous emitter and the contiguous polycrystalline silicon base contact cooperating to provide for each of said transistors a Ft of not less than about 3 GHz.

Claim 3

The integrated circuit of claim 1 wherein the Early Voltage of each of said transistors is not less than about 20 volts.

Claim 4

The integrated circuit of claim 1 wherein β for each transistor is not less than about 40.

Claim 5

The integrated circuit of claim 1 wherein said transistors are each in a dielectrically isolated island.

Claim 6

The integrated circuit of claim 1 wherein the depth of the base of each of said transistors is substantially the same.

Claim 7

The integrated circuit of claim 1 wherein the lateral width of the base of each of said transistors is substantially the same.

Claim 8

The integrated circuit of claim 1 wherein the depth of the collector of each of said transistors is substantially the same.

Claim 9

The integrated circuit of claim 1 wherein the depth of the heavily doped layer within the collector of each of said transistors is substantially the same.

Claim 10

The integrated circuit of claim 1 wherein the base of each of said transistors includes intrinsic and extrinsic bases; and wherein the area of contact between the emitter of each of said transistors and the associated intrinsic base is limited by a sidewall spacer of nitride underlain by a thin oxide layer in contact with said semiconductor surface.

Claim 11

The integrated circuit of claim 1 wherein the collector of at least one of said transistors includes a first dopant to establish the conductivity thereof and a second dopant to relieve the stress caused by said first dopant.

Claim 12

An integrated circuit along a semiconductor surface comprising: (a) a NPN bipolar transistor having: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity and having a polycrystalline silicon contact; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than 50 volts, and (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a Ft of not less than about 7 GHz; and (b) a PNP transistor.

Claim 13

An integrated circuit along a semiconductor surface comprising: (a) a NPN bipolar transistor having: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity and having a polycrystalline silicon contact; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than 50 volts, and (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a Ft of not less than about 7 GHz; and (b) a PNP transistor.

Claim 14

An integrated circuit along a semiconductor surface comprising: (a) a NPN bipolar transistor comprising: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of Ea, (i) the barrier provided by the polycrystalline silicon emitter contact and (ii) the thickness and doping profile of said emitter and said base cooperating to provide an emitter injection efficiency sufficient to produce a current gain of β, the product of Ea and β being not less than about 5,000 volts, and Ft being not less than about 7 Ghz; and (b) a PNP transistor.

Claim 15

An integrated circuit along a semiconductor surface comprising: (a) a NPN bipolar transistor comprising: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of Ea, (i) the barrier provided by the polycrystalline silicon emitter contact and (ii) the thickness and doping profile of said emitter and said base cooperating to provide an emitter injection efficiency sufficient to produce a current gain of β, the product of Ea and β being not less than about 5,000 volts, and Ft being not less than about 7 Ghz; and (b) a PNP transistor.

Claim 16

An integrated circuit along a semiconductor surface comprising: (a) a NPN bipolar transistor; and (b) a PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity and having a polycrystalline silicon contact; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than about 15 volts, (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a Ft not less than about 3 GHz., and (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage not less than about 12 volts.

Claim 17

An integrated circuit along a semiconductor surface comprising: (a) a NPN bipolar transistor; and (b) a PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity and having a polycrystalline silicon contact; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than about 15 volts, (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a Ft not less than about 3 GHz., and (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage not less than about 12 volts.

Claim 18

An integrated circuit along a semiconductor surface comprising: (a) a NPN bipolar transistor; and (b) a PNP-bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of Ea, (i) the barrier provided by the polycrystalline silicon emitter contact and (ii) the thickness and doping profile of said emitter and said base cooperating to provide an emitter injection efficiency sufficient to produce a current gain of β, the product of Ea and β being not less than about 800 volts; and Ft being not less than about 3 Ghz.

Claim 19

An integrated circuit along a semiconductor surface comprising: (a) a NPN bipolar transistor; and (b) a PNP-bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of Ea, (i) the barrier provided by the polycrystalline silicon emitter contact and (ii) the thickness and doping profile of said emitter and said base cooperating to provide an emitter injection efficiency sufficient to produce a current gain of β, the product of Ea and β being not less than about 800 volts; and Ft being not less than about 3 Ghz.

Claim 20

An integrated circuit along a semiconductor surface comprising at least one NPN and one PNP bipolar transistors, each of said transistors having a collector having a more heavily doped layer therein, a base with an intrinsic portion and an emitter with a polycrystalline silicon contact, wherein the contact between the emitter of each of said transistors and the associated intrinsic base is limited by a sidewall spacer of nitride underlain by a thin oxide layer in contact with said semiconductor surface.

Claim 21

An integrated circuit along a semiconductor surface comprising at least one NPN and one PNP bipolar transistors, each of said transistors having a collector having a more heavily doped layer therein, a base with an intrinsic portion and an emitter with a polycrystalline silicon contact, wherein the contact between the emitter of each of said transistors and the associated intrinsic base is limited by a sidewall spacer of nitride underlain by a thin oxide layer in contact with said semiconductor surface.

Claim 22

A integrated circuit along a semiconductor surface comprising: (a) a NPN bipolar transistor having: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity, and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than about 50 volts; and (b) a PNP transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity, and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than about 15 volts.

Claim 23

A integrated circuit along a semiconductor surface comprising: (a) a NPN bipolar transistor having: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity, and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than about 50 volts; and (b) a PNP transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity, and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than about 15 volts.

Claim 24

A integrated circuit along a semiconductor surface comprising: (a) a NPN bipolar transistor having: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a frequency response of not less than about 5 GHz; and (b) a PNP transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity, and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a frequency response of at least 3 GHz., and (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage of not less than about 8 volts.

Claim 25

A integrated circuit along a semiconductor surface comprising: (a) a NPN bipolar transistor having: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a frequency response of not less than about 5 GHz; and (b) a PNP transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity, and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a frequency response of at least 3 GHz., and (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage of not less than about 8 volts.

Claim 26

A NPN bipolar transistor comprising: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity and having a polycrystalline silicon contact; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than 60 volts, and (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a Ft of at least 7 GHz.

Claim 27

A NPN bipolar transistor comprising: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity and having a polycrystalline silicon contact; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than 60 volts, and (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a Ft of at least 7 GHz.

Claim 28

A NPN bipolar transistor comprising: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of Ea, and the barrier provided by the polycrystalline silicon emitter contact and the thickness and doping profile of said emitter and said base cooperating to provide an emitter injection efficiency sufficient to produce a current gain of β, where the product of Ea and β is at least 5,000 volts.

Claim 29

A NPN bipolar transistor comprising: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of Ea, and the barrier provided by the polycrystalline silicon emitter contact and the thickness and doping profile of said emitter and said base cooperating to provide an emitter injection efficiency sufficient to produce a current gain of β, where the product of Ea and β is at least 5,000 volts.

Claim 30

A NPN bipolar transistor comprising: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base with an intrinsic portion doped to a net P conductivity; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the contact between the emitter of each of said transistors and the associated intrinsic base being limited by a sidewall spacer of nitride underlain by a thin oxide layer in contact with said intrinsic base.

Claim 31

A NPN bipolar transistor comprising: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base with an intrinsic portion doped to a net P conductivity; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the contact between the emitter of each of said transistors and the associated intrinsic base being limited by a sidewall spacer of nitride underlain by a thin oxide layer in contact with said intrinsic base.

Claim 32

A NPN bipolar transistor comprising a collector having a more heavily doped layer therein, a base with a polycrystalline silicon contact and an emitter with a polycrystalline silicon contact, the thickness of each base and the contiguous emitter and the doping profiles thereof cooperating to provide an Early Voltage not less than about 60 volts, (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage of not less than about 12 volts; and the contact between the emitter of each of said transistors and the associated intrinsic base being limited by a sidewall spacer of nitride underlain by a thin oxide layer in contact with said intrinsic base.

Claim 33

A NPN bipolar transistor comprising a collector having a more heavily doped layer therein, a base with a polycrystalline silicon contact and an emitter with a polycrystalline silicon contact, the thickness of each base and the contiguous emitter and the doping profiles thereof cooperating to provide an Early Voltage not less than about 60 volts, (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage of not less than about 12 volts; and the contact between the emitter of each of said transistors and the associated intrinsic base being limited by a sidewall spacer of nitride underlain by a thin oxide layer in contact with said intrinsic base.

Claim 34

A NPN bipolar transistor comprising: a base with a polycrystalline silicon contact, an emitter with a polycrystalline silicon contact; and a collector having a more heavily doped layer therein, said collector having a total depth between about 2.0 and 4.0μ and a base to the more heavily doped layer depth between about 0.7 and 1.5μ, said transistor having at least one of (i) an Ea not less than about 60 volts and (ii) an Eaβ not less than about 6,000 volts.

Claim 35

A NPN bipolar transistor comprising: a base with a polycrystalline silicon contact, an emitter with a polycrystalline silicon contact; and a collector having a more heavily doped layer therein, said collector having a total depth between about 2.0 and 4.0μ and a base to the more heavily doped layer depth between about 0.7 and 1.5μ, said transistor having at least one of (i) an Ea not less than about 60 volts and (ii) an Eaβ not less than about 6,000 volts.

Claim 36

A NPN bipolar transistor comprising: a base, an emitter with a polycrystalline silicon contact; and a collector having a net doping concentration between about 3×10 15 and about 9×10 15 cm -3 with a more heavily doped layer therein, said transistor having a Ft not less than about 7 Ghz.

Claim 37

A NPN bipolar transistor comprising: a base, an emitter with a polycrystalline silicon contact; and a collector having a net doping concentration between about 3×10 15 and about 9×10 15 cm -3 with a more heavily doped layer therein, said transistor having a Ft not less than about 7 Ghz.

Claim 38

A NPN bipolar transistor comprising: a base with boron as a dopant therein, an emitter with a polycrystalline silicon contact; and a collector with a more heavily doped layer therein containing phosphorus as a dopant therein, said transistor having at least one of (i) an Ea not less than about 60 volts and (ii) an Eaβ not less than about 6,000 volts.

Claim 39

A NPN bipolar transistor comprising: a base with boron as a dopant therein, an emitter with a polycrystalline silicon contact; and a collector with a more heavily doped layer therein containing phosphorus as a dopant therein, said transistor having at least one of (i) an Ea not less than about 60 volts and (ii) an Eaβ not less than about 6,000 volts.

Claim 40

A NPN bipolar transistor comprising: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage of not less than about 12 volts, and said transistor having at least one of (i) an Ea not less than about 60 volts and (ii) an Eaβ not less than about 6,000 volts.

Claim 41

A NPN bipolar transistor comprising: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage of not less than about 12 volts, and said transistor having at least one of (i) an Ea not less than about 60 volts and (ii) an Eaβ not less than about 6,000 volts.

Claim 42

A NPN bipolar transistor comprising: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the ratio of net dopant concentration in said base to the net dopant concentration in said collector being not less than about 50, and (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of the portion of said base underlying said emitter and (iii) the resistance of said base between said emitter and said base contact cooperating to provide a Ft of not less than about 5 GHz.

Claim 43

A NPN bipolar transistor comprising: a collector doped to a net N conductivity and having a more heavily N doped layer buried therein; a base doped to a net P conductivity; and an emitter doped to a net N conductivity and having a polycrystalline silicon contact, the ratio of net dopant concentration in said base to the net dopant concentration in said collector being not less than about 50, and (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of the portion of said base underlying said emitter and (iii) the resistance of said base between said emitter and said base contact cooperating to provide a Ft of not less than about 5 GHz.

Claim 44

A PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity and having a polycrystalline silicon contact; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than about 15 volts, (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a Ft of not less than about 3 GHz., and (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage not less than about 12 volts.

Claim 45

A PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity and having a polycrystalline silicon contact; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than about 15 volts, (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a Ft of not less than about 3 GHz., and (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage not less than about 12 volts.

Claim 46

A PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of Ea, the barrier provided by the polycrystalline silicon emitter contact and the thickness and doping profile of said emitter and said base cooperating to provide an emitter injection efficiency sufficient to produce a current gain of β, where the product of Ea and β is not less than about 800 volts and Ft is not less than about 3 Ghz.

Claim 47

A PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of Ea, the barrier provided by the polycrystalline silicon emitter contact and the thickness and doping profile of said emitter and said base cooperating to provide an emitter injection efficiency sufficient to produce a current gain of β, where the product of Ea and β is not less than about 800 volts and Ft is not less than about 3 Ghz.

Claim 48

A PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the contact between said emitter and the portion of said base in contact therewith being limited by a sidewall spacer of nitride underlain by a thin oxide layer in contact with said base, and (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a Ft of not less than about 3 GHz.

Claim 49

A PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the contact between said emitter and the portion of said base in contact therewith being limited by a sidewall spacer of nitride underlain by a thin oxide layer in contact with said base, and (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of said base underlying said emitter and (iii) the resistance of said base between said emitter and said polycrystalline silicon base contact cooperating to provide a Ft of not less than about 3 GHz.

Claim 50

A PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity and having a polycrystalline silicon contact; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than about 20 volts, and (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage not less than about 12.

Claim 51

A PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity and having a polycrystalline silicon contact; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of not less than about 20 volts, and (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage not less than about 12.

Claim 52

A PNP bipolar transistor comprising: a base with a polycrystalline silicon contact, an emitter with a polycrystalline silicon contact; and a collector having a more heavily doped layer therein, said collector having a total depth between about 2.0 and 4.0μ and a base to the more heavily doped layer depth between about 0.7 and 1.5μ, said transistor having an Ea not less than about 20 volts.

Claim 53

A PNP bipolar transistor comprising: a base with a polycrystalline silicon contact, an emitter with a polycrystalline silicon contact; and a collector having a more heavily doped layer therein, said collector having a total depth between about 2.0 and 4.0μ and a base to the more heavily doped layer depth between about 0.7 and 1.5μ, said transistor having an Ea not less than about 20 volts.

Claim 54

A PNP bipolar transistor comprising: a base, an emitter with a polycrystalline silicon contact; and a collector having a net doping concentration between about 6×10 15 and about 2×10 17 cm -3 with a more heavily doped layer therein, said transistor having a Ft not less than about 3 Ghz.

Claim 55

A PNP bipolar transistor comprising: a base, an emitter with a polycrystalline silicon contact; and a collector having a net doping concentration between about 6×10 15 and about 2×10 17 cm -3 with a more heavily doped layer therein, said transistor having a Ft not less than about 3 Ghz.

Claim 56

A PNP bipolar transistor comprising: a base with phosphorus as a dopant therein, an emitter with a polycrystalline silicon contact; and a collector with a more heavily doped layer therein containing boron as a dopant therein, said transistor having an Ea not less than about 20 volts.

Claim 57

A PNP bipolar transistor comprising: a base with phosphorus as a dopant therein, an emitter with a polycrystalline silicon contact; and a collector with a more heavily doped layer therein containing boron as a dopant therein, said transistor having an Ea not less than about 20 volts.

Claim 58

A PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity and having a polycrystalline silicon contact; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of Ea, the barrier provided by the polycrystalline silicon emitter contact and the thickness and doping profile of said emitter and said base cooperating to provide an emitter injection efficiency sufficient to produce a current gain of β, where the product of Ea and β is not less than about 800 volts, and (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage not less than about 12 volts.

Claim 59

A PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity and having a polycrystalline silicon contact; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the thickness of said base and said emitter and the doping profiles thereof cooperating to provide an Early Voltage of Ea, the barrier provided by the polycrystalline silicon emitter contact and the thickness and doping profile of said emitter and said base cooperating to provide an emitter injection efficiency sufficient to produce a current gain of β, where the product of Ea and β is not less than about 800 volts, and (i) the doping profile of said collector in the region immediately adjacent said base and (ii) the thickness and doping profile of said base cooperating to provide a collector-to-emitter breakdown voltage not less than about 12 volts.

Claim 60

A PNP bipolar transistor comprising: a base with a polycrystalline silicon contact, an emitter with a polycrystalline silicon contact; and a collector having a more heavily doped layer therein, said collector having a total depth between about 2.0 and 4.0μ and a base to more heavily doped layer depth between about 0.7 and 1.5μ, said transistor having an Eaβ not less than about 800 volts.

Claim 61

A PNP bipolar transistor comprising: a base with a polycrystalline silicon contact, an emitter with a polycrystalline silicon contact; and a collector having a more heavily doped layer therein, said collector having a total depth between about 2.0 and 4.0μ and a base to more heavily doped layer depth between about 0.7 and 1.5μ, said transistor having an Eaβ not less than about 800 volts.

Claim 62

A PNP bipolar transistor comprising: a base with phosphorus as a dopant therein, an emitter with a polycrystalline silicon contact; and a collector with a more heavily doped layer therein containing boron as a dopant therein, said transistor having an Eaβ not less than about 800 volts.

Claim 63

A PNP bipolar transistor comprising: a base with phosphorus as a dopant therein, an emitter with a polycrystalline silicon contact; and a collector with a more heavily doped layer therein containing boron as a dopant therein, said transistor having an Eaβ not less than about 800 volts.

Claim 64

A PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the ratio of net dopant concentration in said base to the net dopant concentration in said collector being not less than about 50, (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of the portion of said base underlying said emitter and (iii) the resistance of said base between said emitter and said base contact cooperating to provide a Ft of not less than about 3 GHz; and a collector-to-emitter breakdown voltage of not less than about 12 volts.

Claim 65

A PNP bipolar transistor comprising: a collector doped to a net P conductivity and having a more heavily P doped layer buried therein; a base doped to a net N conductivity; and an emitter doped to a net P conductivity and having a polycrystalline silicon contact, the ratio of net dopant concentration in said base to the net dopant concentration in said collector being not less than about 50, (i) the thickness of said base and the doping profile thereof, (ii) the geometry and doping profile of the portion of said base underlying said emitter and (iii) the resistance of said base between said emitter and said base contact cooperating to provide a Ft of not less than about 3 GHz; and a collector-to-emitter breakdown voltage of not less than about 12 volts.

Claim 66

An integrated circuit along a semiconductor surface comprising at least one NPN and one PNP bipolar transistors, each of said transistors having a collector having a more heavily doped layer therein, a base with a polycrystalline silicon contact and an emitter with a polycrystalline silicon contact, where: the more heavily doped layers are doped with a first dopant to establish the conductivity thereof, said first dopant being phosphorous in the NPN transistor and said first dopant being boron in the PNP transistor, the ratio of the phosphorous to boron dopant concentrations being between about 0.5 and 2.0, so that the depths of the collectors of each of said transistors are substantially the same and the distance between the base and the more heavily doped layers of each of said transistors are substantially the same.

Claim 67

An integrated circuit along a semiconductor surface comprising at least one NPN and one PNP bipolar transistors, each of said transistors having a collector having a more heavily doped layer therein, a base with a polycrystalline silicon contact and an emitter with a polycrystalline silicon contact, where: the more heavily doped layers are doped with a first dopant to establish the conductivity thereof, said first dopant being phosphorous in the NPN transistor and said first dopant being boron in the PNP transistor, the ratio of the phosphorous to boron dopant concentrations being between about 0.5 and 2.0, so that the depths of the collectors of each of said transistors are substantially the same and the distance between the base and the more heavily doped layers of each of said transistors are substantially the same.

Claim 68

The integrated circuit of claim 38 wherein the heavily doped layers of said transistors include a second dopant to relieve the stress caused by said first dopant, in each of the transistors the atomic radius of one of said two dopants is larger than the atomic radius of the collector semiconductor crystal and the atomic radius of the other of said two dopant is smaller than the atomic radius of the collector semiconductor crystal.

Claim 69

The integrated circuit of claim 39 wherein the dopant concentration of said second dopant is about one tenth to two tenths the dopant concentration of said first dopant.