US5664122A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for sequencing buffers for fast transfer of data between buses
Assignee: Intel Corp
•
Filing: 1996-03-20
•
Granted: 1997-09-02
•
Expires: 2016-03-20
Abstract
Abstract A buffer circuit for transferring data between a first slower narrower computer bus and a second wider faster computer bus which buffer circuit includes first and second buffers each capable of storing a plurality of bytes of data equivalent to the width of the second bus, a single address register for holding an address which represents data in either of the two buffers, the lowest order bit of the address register indicating to which one of the two buffers data is being written, first and second registers for storing indications of valid data in the first and second buffers, and a control circuit for controlling the filling of the first and the second buffers in accordance with the byte addresses furnished and the flushing of the first and the second buffers whenever a most significant byte of a buffer has valid data, whenever an attempt is made to write to a buffer address containing valid data, and whenever an attempt is made to load data to a buffer address different than an address in the address register so that sequences of bytes of data are typically accumulated in order in one buffer until an amount of data equal to that which may be transferred on the second wider faster bus is accumulated and then that buffer is flushed to the second wider faster bus while the other buffer is loaded with new data, and so that valid data is not overwritten even though non-sequential addresses are loaded.
Inventors
- 👤 Jeffrey L. Rabe
- 👤 Sathyamurthi Sadhasivan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:29
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/405; G06F13/4059
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
379 words
A computer system comprising: first and second buses, the first bus operating at a faster data rate relative to the second bus; a central processing unit (CPU); a main memory; a primary bridge circuit for transferring data between the CPU, the main memory, and the first bus; a secondary bridge circuit for transferring data between the first and second buses, the secondary bridge circuit including a first interface unit having an interface buffer coupled to the first bus; a second interface unit coupled to the second bus; and a data buffer circuit coupled to the first and second interface units, the data buffer circuit comprising: first and second buffers each having a plurality of data byte storage locations storing data from a plurality of components on the second bus; an address register storing a data address provided by the second interface unit and a single bit which changes independently of the data address, the single bit indicating that a data byte is to be written to the first buffer or to the second buffer, the single bit changing to an opposite value each time a next data address is stored in the address register, the next data address sometimes being sequential with respect the data address and sometimes not being sequential with respect to the data address; a register storing a pair of bits for indicating a data byte storage location of the first or second buffer to which the data byte is to be written; first and second registers each having a plurality of valid bits, each valid bit corresponding to a data byte storage location of the first and second buffers, respectively; means for controlling the transfer of data from the secondary bus to the first or second buffer according to the data address provided by the second interface unit, and for flushing the first or second buffers when one of the data byte storage locations of the first or second buffer is filled, the data address changes, and the interface buffer is empty, or alternatively, when a valid bit corresponds to one of the data byte storage locations of the first or second buffer, the valid data byte is not stored in the interface buffer, and the data address changes by more than the single bit.
Claim 2
Dependent Claim
379 words
A computer system comprising: first and second buses, the first bus operating at a faster data rate relative to the second bus; a central processing unit (CPU); a main memory; a primary bridge circuit for transferring data between the CPU, the main memory, and the first bus; a secondary bridge circuit for transferring data between the first and second buses, the secondary bridge circuit including a first interface unit having an interface buffer coupled to the first bus; a second interface unit coupled to the second bus; and a data buffer circuit coupled to the first and second interface units, the data buffer circuit comprising: first and second buffers each having a plurality of data byte storage locations storing data from a plurality of components on the second bus; an address register storing a data address provided by the second interface unit and a single bit which changes independently of the data address, the single bit indicating that a data byte is to be written to the first buffer or to the second buffer, the single bit changing to an opposite value each time a next data address is stored in the address register, the next data address sometimes being sequential with respect the data address and sometimes not being sequential with respect to the data address; a register storing a pair of bits for indicating a data byte storage location of the first or second buffer to which the data byte is to be written; first and second registers each having a plurality of valid bits, each valid bit corresponding to a data byte storage location of the first and second buffers, respectively; means for controlling the transfer of data from the secondary bus to the first or second buffer according to the data address provided by the second interface unit, and for flushing the first or second buffers when one of the data byte storage locations of the first or second buffer is filled, the data address changes, and the interface buffer is empty, or alternatively, when a valid bit corresponds to one of the data byte storage locations of the first or second buffer, the valid data byte is not stored in the interface buffer, and the data address changes by more than the single bit.
Claim 3
Dependent Claim
32 words
The computer system of claim 1 wherein the control means provides a signal to the second interface unit stalling the transfer of data when both the first and second buffers are full.
Claim 4
Dependent Claim
22 words
The computer system of claim 2 wherein the signal is provided only until both the first and second buffers have been flushed.
Claim 5
Dependent Claim
20 words
The computer system of claim 1 wherein the single bit comprises the third least significant bit of the data address.
Claim 6
Dependent Claim
24 words
The computer system of claim 4 wherein the pair of bits comprises the first and second least significant bits appended to the data address.
Claim 7
Dependent Claim
32 words
The computer system of claims 1, 2, 3, 4 or 5 wherein the plurality of data byte storage locations comprise four storage locations and the plurality of valid bits comprise four bits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-01 | 2001-03-03 | 2001-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-01 | 2005-03-03 | 2005-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-01 | 2009-03-03 | 2009-09-02 | $7700.00 | Window Closed / Lapsed |