Circuit and method for correcting phase error in a multiplier circuit

Claim 3

The method of claim 1, wherein an amplitude of the phase error signal is substantially equal to an amplitude of the correction signal.

Claim 4

The method of claim 1, wherein the step of multiplying the first signal by the second signal includes a step of routing the first signal through a first signal path to induce the propagation delay in the first signal.

Claim 5

The method of claim 3 wherein the step of delaying the second signal includes a step of routing the second signal through a second signal path.

Claim 6

The method of claim 4, further comprising a step of matching the second signal path to the first signal path.

Claim 7

The method of claim 5, wherein the step of producing the second multiplication signal includes producing the second multiplication signal having the same polarity as the first multiplication signal.

Claim 8

An integrated phase detector, comprising: a multiplier having an input coupled for receiving a first signal, a first signal path routing a second signal for multiplying by the first signal, and an output providing a first multiplication signal indicative of a phase between the first and second signals, where the first signal path introduces a phase shift in the second signal that generates a phase error in the first multiplication signal at the output; a second signal path coupled for delaying the first signal to introduce the phase shift in the first signal at an output; a multiplication stage having a first input coupled for receiving the second signal, a second input coupled to the output of the second signal path and an output providing a second multiplication signal indicative of the phase between the first and second signals, where the second multiplication signal includes a correction signal representative of the phase shift, such that the phase error and the correction signal have opposite polarities; and a summing circuit having a first input coupled to the output of the multiplier, a second input coupled to the output of the multiplication stage, and an output providing a phase detected signal such that the correction signal offsets the phase error.

Claim 9

An integrated phase detector, comprising: a multiplier having an input coupled for receiving a first signal, a first signal path routing a second signal for multiplying by the first signal, and an output providing a first multiplication signal indicative of a phase between the first and second signals, where the first signal path introduces a phase shift in the second signal that generates a phase error in the first multiplication signal at the output; a second signal path coupled for delaying the first signal to introduce the phase shift in the first signal at an output; a multiplication stage having a first input coupled for receiving the second signal, a second input coupled to the output of the second signal path and an output providing a second multiplication signal indicative of the phase between the first and second signals, where the second multiplication signal includes a correction signal representative of the phase shift, such that the phase error and the correction signal have opposite polarities; and a summing circuit having a first input coupled to the output of the multiplier, a second input coupled to the output of the multiplication stage, and an output providing a phase detected signal such that the correction signal offsets the phase error.

Claim 10

The integrated phase detector of claim 7, wherein the second signal path is matched to the first signal path.

Claim 11

The integrated phase detector of claim 8 wherein an amplitude of the correction signal is substantially equal to an amplitude of the phase error.

Claim 12

The integrated phase detector of claim 9, wherein the first and second multiplication signals have the same polarity.

Claim 13

The integrated phase detector of claim 7, wherein the first signal path includes a first differential amplifier having an input coupled for receiving the second signal.

Claim 14

The integrated phase detector of claim 11, wherein the multiplier includes a first doubly balanced amplifier having a first input coupled to an output of the first signal path, and a second input and an output respectively coupled to the input and output of the multiplier.

Claim 15

The integrated phase detector of claim 12, wherein the second signal path includes a second differential amplifier having an input coupled for receiving the first signal and an output coupled to an output of the second signal path.

Claim 16

The integrated phase detector of claim 13, wherein the multiplication stage comprises a second doubly balanced amplifier having first and second inputs and an output respectively coupled to the first and second inputs and the output of the multiplication stage.

Claim 17

An integrated circuit, comprising: a voltage controllable oscillator (VCO) for producing a quadrature signal at an output in response to a control signal; a phase detector, including (1) a multiplier having an input coupled for receiving a first signal, a first signal path routing a second signal for multiplying by the first signal, and an output providing a first multiplication signal indicative of a phase between the first and second signals, where the first signal path introduces a phase shift in the second signal that generates a phase error in the first multiplication signal at the output; (2) a second signal path coupled for delaying the first signal to introduce a phase shift in the first signal at an output; (3) a multiplication stage having a first input coupled for receiving the second signal, a second input coupled to the output of the second signal path and an output providing a second multiplication signal indicative of the phase between the first and second signals, where the second multiplication signal includes a correction signal representative of the phase shift, such that the phase error and the correction signal have opposite polarities; and (4) a summing circuit having a first input coupled to the output of the multiplier, a second input coupled to the output of the multiplication stage, and an output providing the control signal such that the correction signal offsets the phase error.

Claim 18

An integrated circuit, comprising: a voltage controllable oscillator (VCO) for producing a quadrature signal at an output in response to a control signal; a phase detector, including (1) a multiplier having an input coupled for receiving a first signal, a first signal path routing a second signal for multiplying by the first signal, and an output providing a first multiplication signal indicative of a phase between the first and second signals, where the first signal path introduces a phase shift in the second signal that generates a phase error in the first multiplication signal at the output; (2) a second signal path coupled for delaying the first signal to introduce a phase shift in the first signal at an output; (3) a multiplication stage having a first input coupled for receiving the second signal, a second input coupled to the output of the second signal path and an output providing a second multiplication signal indicative of the phase between the first and second signals, where the second multiplication signal includes a correction signal representative of the phase shift, such that the phase error and the correction signal have opposite polarities; and (4) a summing circuit having a first input coupled to the output of the multiplier, a second input coupled to the output of the multiplication stage, and an output providing the control signal such that the correction signal offsets the phase error.

Claim 19

The integrated circuit of claim 15, further comprising a loop filter for limiting a bandwidth of the control signal.

Claim 20

The integrated circuit of claim 16, wherein the second signal path is matched to the first signal path.

Claim 21

The integrated circuit of claim 17, wherein an amplitude of the correction signal is substantially equal to an amplitude of the phase error.

Claim 22

The integrated circuit of claim 18, wherein the first and second multiplication signals have the same polarity.

Claim 25

An integrated phase detector, comprising: a first multiplier having a first input coupled for receiving a first signal, a second input coupled for receiving a second signal, and an output for providing a first multiplied signal, where the first multiplier has a first propagation delay from the first input to the output and a second propagation delay from the second input to the output longer than the first propagation delay of the first multiplier; a second multiplier having a first input coupled for receiving the second signal, a second input coupled for receiving the first signal, and an output for providing a second multiplied signal, where the second multiplier has a first propagation delay from the first input to the output and a second propagation delay from the second input to the output longer than the first propagation delay of the second multiplier; and a summing circuit having a first input coupled to the output of the first multiplier, a second input coupled to the output of the second multiplier, and an output providing a phase detected signal.

Claim 26

An integrated phase detector, comprising: a first multiplier having a first input coupled for receiving a first signal, a second input coupled for receiving a second signal, and an output for providing a first multiplied signal, where the first multiplier has a first propagation delay from the first input to the output and a second propagation delay from the second input to the output longer than the first propagation delay of the first multiplier; a second multiplier having a first input coupled for receiving the second signal, a second input coupled for receiving the first signal, and an output for providing a second multiplied signal, where the second multiplier has a first propagation delay from the first input to the output and a second propagation delay from the second input to the output longer than the first propagation delay of the second multiplier; and a summing circuit having a first input coupled to the output of the first multiplier, a second input coupled to the output of the second multiplier, and an output providing a phase detected signal.