Hardware filter circuit and address circuitry for MPEG encoded data

Claim 1

A data processing system for decoding and filtering encoded data retrieved from a first buffer circuit and outputting the processed data to a second buffer circuit, comprising: circuitry for retrieving encoded sample data and scale factor information from within a first block of encoded data stored in the first buffer; circuitry for dequantizing the sample data to form dequantized sample data using the scale factor information; first circuitry for storing the dequantized sample data; circuitry for transforming the dequantized sample data using a fast cosine transform process to form transformed dequantized sample data; second circuitry for storing the transformed dequantized sample data; circuitry for filtering the transformed dequantized sample data; a plurality of circuits for storing scale factors and coefficients; circuitry for addressing said first and second circuits for storing and said plurality of circuits for storing by providing a plurality of addresses derived from a single state value; and wherein said circuitry for addressing further comprises: a sequence generator which outputs said state value; an address storage circuit connected to said sequence generator which outputs an index value in response to said state value; said first buffer outputs said scale factor information in response to said state value; and circuitry to combine said state value, said index value and said scale factor to form a plurality of addresses for accessing said second circuit for storing and said plurality of circuits for storing.