Scan circuit having a reduced clock signal delay

Claim 2

A scan circuit including: a plurality of stages of cascaded pulse delay transfer circuits, a first stage of said plurality of stages receiving an input pulse signal and outputting to a subsequent stage a given pulse signal, each subsequent stage of said plurality of stages for receiving a given pulse signal from a respective preceding stage, so as to transfer the received pulse signal at a delayed timing in synchronism with a clock signal; and a corresponding number of output buffers each for receiving an output of the pulse delay transfer circuit of a corresponding stage so that respective outputs of said cascaded pulse delay transfer circuits are parallel-outputted through said output buffers, respectively, each of said pulse delay transfer circuits including a single-phase-clock-controlled complementary-metal-oxide-semiconducting (CMOS) inverter controlled with only a single-phase-clock, wherein said single-phase-clock-controlled inverter includes first and second P-channel insulated gate transistors and first and second N-channel insulated gate transistors cascaded between a voltage supply voltage and ground, gates of said second P-channel insulated gate transistors and said first N-channel insulated gate transistors being connected in common to receive said given pulse signal, and drains of said second P-channel insulated gate transistors and said first N-channel insulated gate transistors being connected in common to generate an output signal, gates of said first P-channel insulated gate transistors and said second N-channel insulated gate transistors being connected to receive the same single-phase-clock.

Claim 3

A scan circuit including: a plurality of stages of cascaded pulse delay transfer circuits, a first stage of said plurality of stages receiving an input pulse signal and outputting to a subsequent stage a given pulse signal, each subsequent stage of said plurality of stages for receiving a given pulse signal from a respective preceding stage, so as to transfer the received pulse signal at a delayed timing in synchronism with a clock signal; and a corresponding number of output buffers each for receiving an output of the pulse delay transfer circuit of a corresponding stage so that respective outputs of said cascaded pulse delay transfer circuits are parallel-outputted through said output buffers, respectively, each of said pulse delay transfer circuits including a single-phase-clock-controlled complementary-metal-oxide-semiconducting (CMOS) inverter controlled with only a single-phase-clock, and a logic gate circuit for receiving the output of the single-phase-clock-controlled CMOS inverter of the same stage and said single-phase-clock applied to the single-phase-clock-controlled CMOS inverter of the same stage, outputs of respective logic gate circuits of the pulse delay transfer circuits being outputted in parallel to one another to respective output buffers of corresponding stages, wherein said single-phase-clock-controlled inverter includes first and second P-channel insulated gate transistors and first and second N-channel insulated gate transistors cascaded between a voltage supply voltage and ground, gates of said second P-channel insulated gate transistors and said first N-channel insulated gate transistors being connected in common to receive said given pulse signal, and drains of said second P-channel insulated gate transistors and said first N-channel insulated gate transistors being connected in common to generate an output signal, gates of said first P-channel insulated gate transistors and said second N-channel insulated gate transistors being connected to receive the same single-phase-clock.

Claim 4

A scan circuit including: a plurality of stages of cascaded pulse delay transfer circuits, a first stage of said plurality of stages receiving an input pulse signal and outputting to a subsequent stage a given pulse signal, each subsequent stage of said plurality of stages for receiving a given pulse signal from a respective preceding stage, so as to transfer the received pulse signal at a delayed timing in synchronism with a clock signal; and a corresponding number of output buffers each for receiving an output of the pulse delay transfer circuit of a corresponding stage so that respective outputs of said cascaded pulse delay transfer circuits are parallel-outputted through said output buffers, respectively, each of said pulse delay transfer circuits including a single-phase-clock-controlled complementary-metal-oxide-semiconducting (CMOS) inverter controlled with only a single-phase-clock, and a logic gate circuit for receiving the output of the single-phase-clock-controlled CMOS inverter of the same stage and said single-phase-clock applied to the single-phase-clock-controlled CMOS inverter of the same stage, outputs of respective logic gate circuits of the pulse delay transfer circuits being outputted in parallel to one another to respective output buffers of corresponding stages, wherein said single-phase-clock-controlled inverter includes first and second P-channel insulated gate transistors and first and second N-channel insulated gate transistors cascaded between a voltage supply voltage and ground, gates of said second P-channel insulated gate transistors and said first N-channel insulated gate transistors being connected in common to receive said given pulse signal, and drains of said second P-channel insulated gate transistors and said first N-channel insulated gate transistors being connected in common to generate an output signal, gates of said first P-channel insulated gate transistors and said second N-channel insulated gate transistors being connected to receive the same single-phase-clock.

Claim 5

A scan circuit claimed in claim 2, wherein said logic gate circuit comprises a NOR gate in an odd-numbered stage and a NAND gate in an even-numbered stage, and wherein said output buffer having an input connected to an output of said NOR gate generates a non-inverted output and said output buffer having an input connected to an output of said NAND gate generates an inverted output.

Claim 6

A scan circuit including: a plurality of stages of cascaded pulse delay transfer circuits, a first stage of said plurality of stages receiving an input pulse signal and outputting to a subsequent stage a given pulse signal, each subsequent stage of said plurality of stages for receiving a given pulse signal from a respective preceding stage, so as to transfer the received pulse signal at a delayed timing in synchronism with a clock signal; and a corresponding number of output buffers each for receiving an output of the pulse delay transfer circuit of a corresponding stage so that respective outputs of said cascaded pulse delay transfer circuits are parallel-outputted through said output buffers, respectively, each of said pulse delay transfer circuits including a single-phase-clock-controlled complementary-metal-oxide-semiconducting (CMOS) inverter controlled with only a single-phase-clock, and a logic gate circuit for receiving an output of the single-phase-clock-controlled CMOS inverter of the same stage and an output of the single-phase-clock-controlled CMOS inverter of a next stage, each said logic gate circuit outputting a scan signal, outputs of respective logic gate circuits of the pulse delay transfer circuits being outputted in parallel to one another to respective ones of said output buffers, wherein said single-phase-clock-controlled inverter includes first and second P-channel insulated gate transistors and first and second N-channel insulated gate transistors cascaded between a voltage supply voltage and ground, gates of said second P-channel insulated gate transistors and said first N-channel insulated gate transistors being connected in common to receive said given pulse signal, and drains of said second P-channel insulated gate transistors and said first N-channel insulated gate transistors being connected in common to generate an output signal, gates of said first P-channel insulated gate transistors and said second N-channel insulated gate transistors being connected to receive the same single-phase-clock.

Claim 7

A scan circuit including: a plurality of stages of cascaded pulse delay transfer circuits, a first stage of said plurality of stages receiving an input pulse signal and outputting to a subsequent stage a given pulse signal, each subsequent stage of said plurality of stages for receiving a given pulse signal from a respective preceding stage, so as to transfer the received pulse signal at a delayed timing in synchronism with a clock signal; and a corresponding number of output buffers each for receiving an output of the pulse delay transfer circuit of a corresponding stage so that respective outputs of said cascaded pulse delay transfer circuits are parallel-outputted through said output buffers, respectively, each of said pulse delay transfer circuits including a single-phase-clock-controlled complementary-metal-oxide-semiconducting (CMOS) inverter controlled with only a single-phase-clock, and a logic gate circuit for receiving an output of the single-phase-clock-controlled CMOS inverter of the same stage and an output of the single-phase-clock-controlled CMOS inverter of a next stage, each said logic gate circuit outputting a scan signal, outputs of respective logic gate circuits of the pulse delay transfer circuits being outputted in parallel to one another to respective ones of said output buffers, wherein said single-phase-clock-controlled inverter includes first and second P-channel insulated gate transistors and first and second N-channel insulated gate transistors cascaded between a voltage supply voltage and ground, gates of said second P-channel insulated gate transistors and said first N-channel insulated gate transistors being connected in common to receive said given pulse signal, and drains of said second P-channel insulated gate transistors and said first N-channel insulated gate transistors being connected in common to generate an output signal, gates of said first P-channel insulated gate transistors and said second N-channel insulated gate transistors being connected to receive the same single-phase-clock.

Claim 8

A scan circuit claimed in claim 4, wherein said logic gate circuit comprises a NOR gate in an odd-numbered stage and a NAND gate in an even-numbered stage, and wherein said output buffer having an input connected to an output of said NOR gate generates a non-inverted output and said output buffer having an input connected to an output of said NAND gate generates an inverted output.

Claim 9

A scan circuit claimed in claim 4, wherein said logic gate circuit comprises a NAND gate, said NAND gate in an odd-numbered stage having a first input connected through an inverter to said output of the single-phase-clock controlled CMOS inverter of the same stage and a second input connected directly to said output of the single-phase-clock controlled CMOS inverter of said next stage, and said NAND gate in an even-numbered stage having a first input connected directly to said output of the single-phase-clock controlled CMOS inverter of the same stage and a second input connected through an inverter to said output of the single-phase-clock controlled CMOS inverter of said next stage, and wherein said output buffer comprises an inverting buffer for generating an inverted signal of an output of said NAND gate of the same stage.

Claim 10

A scan circuit claimed in claim 1, wherein each of said pulse delay transfer circuits comprises only said single-phase-clock-controlled CMOS inverter, and wherein said output buffer circuit connected to said single-phase-clock-controlled CMOS inverter in an odd-numbered stage outputs an inverted output signal, and wherein said output buffer circuit connected to said single-phase-clock-controlled CMOS inverter in an even-numbered stage outputs a non-inverted output signal.

Claim 11

A scan circuit according to claim 1, wherein each of said pulse delay transfer circuits includes a logic gate circuit for receiving an output of the single-phase-clock-controlled CMOS inverter of the same stage and said single-phase-clock applied to the single-phase-clock-controlled CMOS inverter of the same stage.

Claim 12

A scan circuit according to claim 8, wherein said logic gate circuit comprises a NOR gate in an odd-numbered stage, and wherein said output buffer having an input connected to an output of said NOR gate generates a non-inverted output.

Claim 13

A scan circuit according to claim 8, wherein said logic gate circuit comprises a NAND gate in an even-numbered stage, and wherein said output buffer having an input connected to an output of said NAND gate generates an inverted output.

Claim 14

A scan circuit according to claim 1, wherein each of said pulse delay transfer circuits includes a logic gate circuit for receiving the output of the single-phase-clock-controlled CMOS inverter of the same stage.

Claim 15

A scan circuit according to claim 11, wherein each logic gate circuit receives the output of the single-phase-clock-controlled CMOS inverter of a next stage, and outputs a scan signal, outputs of respective logic gate circuits of the pulse delay transfer circuits being outputted in parallel to one another.

Claim 16

A scan circuit according to claim 11, wherein said logic gate circuit comprises a NOR gate in an odd-numbered stage, wherein said output buffer having an input connected an output of said NOR gate generates a non-inverted output.

Claim 17

A scan circuit according to claim 11, wherein said logic gate circuit comprises a NAND gate in an even-numbered stage, and wherein said output buffer having an input connected to an output of said NAND gate generates an inverted output.

Claim 18

A scan circuit according to claim 11, wherein said logic gate circuit comprises a NAND gate, said NAND gate in an odd-numbered stage having a first input connected through an inverter to said output of the single-phase-clock-controlled CMOS inverter of the same stage.

Claim 19

A scan circuit according to claim 1, wherein a clock signal applied to said single-phase-clock-controlled CMOS inverter is a same single clock signal and is the same for all stages of said plurality of stages.

Claim 20

A scan circuit according to claim 1, wherein an output of said first stage of said plurality of stages has a same pulse width as that of a second stage of said plurality of stages.

Claim 21

A scan circuit according to claim 2, wherein an output of said first stage of said plurality of stages has a same pulse width as that of a second stage of said plurality of stages.

Claim 22

A scan circuit according to claim 4, wherein an output of said first stage of said plurality of stages has a same pulse width as that of a second stage of said plurality of stages.