US5652894A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for providing power saving modes to a pipelined processor
Assignee: Intel Corp
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Filing: 1995-09-29
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Granted: 1997-07-29
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Expires: 2015-09-29
Abstract
Abstract A clock and reset unit for providing power saving modes to a pipelined microprocessor and for guaranteeing that power saving instruction is the last to be executed before the clocks stop, upon wake-up the next instruction executed is the first instruction in the interrupt service routine (ISR) and that upon return from the ISR, the instruction immediately following the power saving instruction is executed. A register is provided in the clock and reset unit for initiating a power saving mode. A software programmer selects a particular power saving mode by setting a corresponding bit in this register (i.e., writing a predetermined value to this register). A processor stalling signal generator for generating a signal that indicates to the processor that the peripheral is not ready to process a processor request (thereby causing the processor to insert wait states until the peripheral is ready) is provided. The clock and reset unit is also provided a signal from an interrupt handler indicating that the processor will be executing the ISR upon leaving the power save instruction. In response to this signal, the clock and reset unit de-assert the wait state request and brought the processor out of the power saving instruction.
Inventors
- 👤 King Seng Hu
- 👤 Vui Yong Liew
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:26
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4418; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
209 words
In a computer system having a pipelined processor, said processor receiving a plurality of clock signals, a method for providing power saving modes to the pipelined processor and for guaranteeing that a power save instruction is a last instruction to be executed before the clocks are frozen, that upon wake-up a next instruction executed is a first instruction in an interrupt service routine (ISR) and that upon return from the ISR, an instruction immediately following a power saving instruction is executed, said method comprising the steps of: a) detecting a write to a power saving mode register; b) if a write to the power saving mode register is detected, stalling the processor, else return to step (a); c) determining if a power saving mode bit is set as a result of the write; d) if the power saving mode bit is set, continue stalling the processor and freeze the clocks, else restart the processor and return to step (a); e) determining if an interrupt request is active and the power saving mode bit is clear; and f) if the interrupt request is active and the power saving mode bit is clear, restart the processor and returning to step (a), else, continue stalling the processor and return to step (f).
Claim 2
Dependent Claim
209 words
In a computer system having a pipelined processor, said processor receiving a plurality of clock signals, a method for providing power saving modes to the pipelined processor and for guaranteeing that a power save instruction is a last instruction to be executed before the clocks are frozen, that upon wake-up a next instruction executed is a first instruction in an interrupt service routine (ISR) and that upon return from the ISR, an instruction immediately following a power saving instruction is executed, said method comprising the steps of: a) detecting a write to a power saving mode register; b) if a write to the power saving mode register is detected, stalling the processor, else return to step (a); c) determining if a power saving mode bit is set as a result of the write; d) if the power saving mode bit is set, continue stalling the processor and freeze the clocks, else restart the processor and return to step (a); e) determining if an interrupt request is active and the power saving mode bit is clear; and f) if the interrupt request is active and the power saving mode bit is clear, restart the processor and returning to step (a), else, continue stalling the processor and return to step (f).
Claim 3
Dependent Claim
23 words
The method of claim 1 wherein the step of stalling the processor includes deactivating the clock signals that are provided to the processor.
Claim 4
Dependent Claim
23 words
The method of claim 1 wherein the step of restarting the processor includes restarting the clock signals that are provided to the processor.
Claim 5
Dependent Claim
15 words
The method of claim 1 wherein the power saving mode bit is a powerdown bit.
Claim 6
Dependent Claim
15 words
The method of claim 1 wherein the power saving mode bit is an idle bit.
Claim 7
Dependent Claim
253 words
In a computer system having a pipelined processor, said processor receiving a plurality of clock signals, said computer system comprising: a) a bus, coupled to the processor, for transferring information; b) a clock and reset unit, coupled to the bus, for providing the plurality of clock signals to the computer system and also a reset signal to the computer system, said clock and reset unit including i) a detection circuit for detecting a write to a power saving mode register, disposed in the clock and reset unit; ii) a stalling circuit, coupled to the detection circuit, for stalling the processor if a write to the power saving mode register is detected by the detection circuit; iii) a first determination circuit for determining if a power saving mode bit is set as a result of a write to the power saving mode register; iv) means, coupled to the first determination circuit, for continuing to stall the processor and freezing the clocks if the power saving mode bit is set and for ceasing to stall the processor if the power saving mode bit is not set; and v) a second determination circuit, coupled to the bus, for determining if an interrupt request is active and if the power saving mode bit is clear, said second determination circuit ceasing to stall the processor and enabling the clocks if the interrupt request is active and the power saving mode bit is clear, and for continuing to freeze the clocks and to stall the processor in the alternative.
Claim 8
Dependent Claim
253 words
In a computer system having a pipelined processor, said processor receiving a plurality of clock signals, said computer system comprising: a) a bus, coupled to the processor, for transferring information; b) a clock and reset unit, coupled to the bus, for providing the plurality of clock signals to the computer system and also a reset signal to the computer system, said clock and reset unit including i) a detection circuit for detecting a write to a power saving mode register, disposed in the clock and reset unit; ii) a stalling circuit, coupled to the detection circuit, for stalling the processor if a write to the power saving mode register is detected by the detection circuit; iii) a first determination circuit for determining if a power saving mode bit is set as a result of a write to the power saving mode register; iv) means, coupled to the first determination circuit, for continuing to stall the processor and freezing the clocks if the power saving mode bit is set and for ceasing to stall the processor if the power saving mode bit is not set; and v) a second determination circuit, coupled to the bus, for determining if an interrupt request is active and if the power saving mode bit is clear, said second determination circuit ceasing to stall the processor and enabling the clocks if the interrupt request is active and the power saving mode bit is clear, and for continuing to freeze the clocks and to stall the processor in the alternative.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-28 | 2001-01-27 | 2001-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-28 | 2005-01-27 | 2005-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-28 | 2009-01-27 | 2009-07-29 | $7700.00 | Window Closed / Lapsed |