Apparatus for preforming discrete-time analog queuing and computing in a communication system

Claim 2

A discrete-time analog queuing element, comprising: N analog signal lines, wherein N is a positive integer; N analog storage lines; N 2 controllable switches, each controllable switch of the N 2 controllable switches coupled between each of the N analog signal lines and each of the N analog storage lines; N charge storage elements, each charge storage element of the N charge storage elements coupled between each of the N analog storage lines and a common circuit node; and N control lines, each control line coupled to N of the N 2 controllable switches, the control lines for controlling the controllable switches such that in response to the control lines being activated in a predetermined sequence, each of the analog storage lines is coupled in turn to each of the analog signal lines in a sequence having a predetermined rotating order, wherein the predetermined rotating order is identical for each of the analog storage lines, except that the sequence corresponding to each of the analog storage lines begins with a different one of the analog signal lines.

Claim 3

The discrete-time analog queuing element of claim 1, wherein an analog signal line of the N analog signal lines is coupled to a reference circuit node for setting a predetermined charge and s resultant voltage on a charge storage element of the N charge storage elements in response to the analog signal line being coupled to the charge storage element through one of the N 2 controllable switches, and wherein at least one of the analog signal lines is an input for receiving at least one discrete-time analog input signal, and wherein at least one of the analog signal lines is an output for delivering at least one discrete-time output signal.

Claim 4

The discrete-time analog queuing element of claim 1, further comprising at least one charge transfer circuit, comprising: an input for receiving an input voltage change; and an output coupled to one of the analog signal lines for delivering thereto a charge proportional to the input voltage change.

Claim 5

The discrete-time analog queuing element of claim 1, further comprising at least one charge transfer circuit, comprising: an input coupled to one of the analog signal lines for receiving therefrom an input voltage change; and an output for providing a charge proportional to the input voltage change.

Claim 6

A discrete-time analog computing element, comprising: an input node coupled to at least one discrete-time analog queuing element for receiving a discrete-time analog input signal; an output node coupled to the at least one discrete-time analog queuing element for providing a computed output signal responsive to the discrete-time analog input signal; a clock and logic circuit coupled to the at least one discrete-time analog queuing element for generating a plurality of control signals activated in a predetermined sequence; and the at least one discrete-time analog queuing element, comprising: N analog signal lines, wherein N is a positive integer; N analog storage lines; N 2 controllable switches, each controllable switch of the N 2 controllable switches coupled between each of the N analog signal lines and each of the N analog storage lines; N charge storage elements, each charge storage element of the N charge storage elements element coupled between each of the N analog storage lines and a common circuit node; and N control lines, each control line coupled to N of the N 2 controllable switches and coupled to the clock and logic circuit, the N control lines for controlling the controllable switches such that in response to the control lines being activated in the predetermined sequence, each of the analog storage lines is coupled in turn to each of the analog signal lines in a sequence having a predetermined rotating order, wherein the predetermined rotating order is identical for each of the analog storage lines, except that the sequence corresponding to each of the analog storage lines begins with a different one of the analog signal lines.

Claim 7

A discrete-time analog computing element, comprising: an input node coupled to at least one discrete-time analog queuing element for receiving a discrete-time analog input signal; an output node coupled to the at least one discrete-time analog queuing element for providing a computed output signal responsive to the discrete-time analog input signal; a clock and logic circuit coupled to the at least one discrete-time analog queuing element for generating a plurality of control signals activated in a predetermined sequence; and the at least one discrete-time analog queuing element, comprising: N analog signal lines, wherein N is a positive integer; N analog storage lines; N 2 controllable switches, each controllable switch of the N 2 controllable switches coupled between each of the N analog signal lines and each of the N analog storage lines; N charge storage elements, each charge storage element of the N charge storage elements element coupled between each of the N analog storage lines and a common circuit node; and N control lines, each control line coupled to N of the N 2 controllable switches and coupled to the clock and logic circuit, the N control lines for controlling the controllable switches such that in response to the control lines being activated in the predetermined sequence, each of the analog storage lines is coupled in turn to each of the analog signal lines in a sequence having a predetermined rotating order, wherein the predetermined rotating order is identical for each of the analog storage lines, except that the sequence corresponding to each of the analog storage lines begins with a different one of the analog signal lines.

Claim 8

The discrete-time analog computing element of claim 5, wherein an analog signal line of the N analog signal lines is coupled to a reference circuit node for setting a predetermined charge and resultant voltage on a charge storage element of the N charge storage elements in response to the analog signal line being coupled to the charge storage element through one of the N 2 controllable switches, and wherein at least one of the analog signal lines is an input for receiving at least one discrete-time analog input signal, and wherein at least one of the analog signal lines is an output for delivering at least one discrete-time output signal.

Claim 9

The discrete-time analog computing element of claim 5, wherein the at least one discrete-time analog queuing element further comprises at least one charge transfer circuit, comprising: an input for receiving an input voltage change; and an output coupled to one of the analog signal lines for delivering thereto a charge proportional to the input voltage change.

Claim 10

The discrete-time analog computing element of claim 5, wherein the at least one discrete-time analog queuing element further comprises at least one charge transfer circuit, comprising: an input coupled to one of the analog signal lines for receiving therefrom an input voltage change; and an output for providing a charge proportional to the input voltage change.

Claim 11

A discrete-time phase locked loop, comprising: a phase error detector having a discrete-time pulse width modulation (DTPWM) output signal, the phase error detector coupled to a reference signal and coupled to a generated signal for detecting a phase difference between the reference signal and the generated signal; and a discrete-time analog computing element, comprising: an input node coupled to the phase error detector and coupled to at least one discrete-time analog queuing element for receiving the DTPWM output signal; an output node coupled to the at least one discrete-time analog queuing element for providing a computed output signal responsive to the DTPWM output signal of the phase error detector; a clock and logic circuit coupled to the at least one discrete-time analog queuing element for generating a plurality of control signals activated in a predetermined sequence; and the at least one discrete-time analog queuing element, comprising: N analog signal lines, wherein N is a positive integer; N analog storage lines; N 2 controllable switches, each controllable switch of the N 2 controllable switches coupled between each of the N analog signal lines and each of the N analog storage lines; N charge storage elements, each charge storage element of the N charge storage elements coupled between each of the N analog storage lines and a common circuit node; and N control lines, each control line coupled to N of the N 2 controllable switches and coupled to the clock and logic circuit, the N control lines for controlling the controllable switches such that in response to the control lines being activated in the predetermined sequence, each of the analog storage lines is coupled to each of the analog signal lines in a sequence having a predetermined rotating order, wherein the predetermined rotating order is identical for each of the analog storage lines, except that the sequence corresponding to each of the analog storage lines begins with a different one of the analog signal lines, wherein the discrete-time phase locked loop further comprises a controlled oscillator coupled to the output node of the descrete-time analog computing element for producing the generated signal.

Claim 12

A discrete-time phase locked loop, comprising: a phase error detector having a discrete-time pulse width modulation (DTPWM) output signal, the phase error detector coupled to a reference signal and coupled to a generated signal for detecting a phase difference between the reference signal and the generated signal; and a discrete-time analog computing element, comprising: an input node coupled to the phase error detector and coupled to at least one discrete-time analog queuing element for receiving the DTPWM output signal; an output node coupled to the at least one discrete-time analog queuing element for providing a computed output signal responsive to the DTPWM output signal of the phase error detector; a clock and logic circuit coupled to the at least one discrete-time analog queuing element for generating a plurality of control signals activated in a predetermined sequence; and the at least one discrete-time analog queuing element, comprising: N analog signal lines, wherein N is a positive integer; N analog storage lines; N 2 controllable switches, each controllable switch of the N 2 controllable switches coupled between each of the N analog signal lines and each of the N analog storage lines; N charge storage elements, each charge storage element of the N charge storage elements coupled between each of the N analog storage lines and a common circuit node; and N control lines, each control line coupled to N of the N 2 controllable switches and coupled to the clock and logic circuit, the N control lines for controlling the controllable switches such that in response to the control lines being activated in the predetermined sequence, each of the analog storage lines is coupled to each of the analog signal lines in a sequence having a predetermined rotating order, wherein the predetermined rotating order is identical for each of the analog storage lines, except that the sequence corresponding to each of the analog storage lines begins with a different one of the analog signal lines, wherein the discrete-time phase locked loop further comprises a controlled oscillator coupled to the output node of the descrete-time analog computing element for producing the generated signal.

Claim 13

The discrete-time phase locked loop of claim 9, wherein an analog signal line of the N analog signal lines is coupled to a reference circuit node for setting a predetermined charge and resultant voltage on a charge storage element of the N charge storage elements in response to the analog signal line being coupled to the charge storage element through one of the N 2 controllable switches, and wherein at least one of the analog signal lines is an input for receiving at least one discrete-time analog input signal, and wherein at least one of the analog signal lines is an output for delivering at least one discrete-time output signal.

Claim 14

The discrete-time phase locked loop of claim 9, wherein the at least one discrete-time analog queuing element further comprises at least one charge transfer circuit, comprising: an input for receiving an input voltage change; and an output coupled to one of the analog signal lines for delivering thereto a charge proportional to the input voltage change.

Claim 15

The discrete-time phase locked loop of claim 9, wherein the at least one discrete-time analog queuing element further comprises at least one charge transfer circuit, comprising: an input coupled to one of the analog signal lines for receiving therefrom an input voltage change; and an output for providing a charge proportional to the input voltage change.

Claim 16

The discrete-time phase locked loop of claim 9, wherein the controlled oscillator produces a desired signal operating at a desired frequency, and wherein the controlled oscillator comprises a frequency divider coupled to the desired signal for frequency dividing the desired signal to produce the generated signal.

Claim 17

A communication receiver, comprising: an antenna for intercepting a signal including information; a receiver element coupled to the antenna for demodulating the signal to derive the information; a processor coupled to the receiver element for processing the information; a synthesizer coupled to the processor for producing a generated signal utilized by the communication receiver, the synthesizer comprising: a reference oscillator for generating a reference signal; and a discrete-time phase locked loop, comprising: a phase error detector having a discrete-time pulse width modulation (DTPWM) output signal, the phase error detector coupled to the reference oscillator for receiving the reference signal and coupled to the generated signal for detecting a phase difference between the reference signal and the generated signal; and a discrete-time analog computing element, comprising: an input node coupled to the phase error detector and coupled to at least one discrete-time analog queuing element for receiving the DTPWM output signal; an output node coupled to the at least one discrete-time analog queuing element for providing a computed output signal responsive to the DTPWM output signal of the phase error detector; a clock and logic circuit coupled to the at least one discrete-time analog queuing element for generating a plurality of control signals activated in a predetermined sequence; and the at least one discrete-time analog queuing element, comprising: N analog signal lines, wherein N is a positive integer; N analog storage lines; N 2 controllable switches, each controllable switch of the N 2 controllable switches coupled between each of the N analog signal lines and each of the N analog storage lines; N charge storage elements, each charge storage element of the N charge storage elements coupled between each of the N analog storage lines and a common circuit node; and N control lines, each control line coupled to N of the N 2 controllable switches and coupled to the clock and logic circuit, the N control lines for controlling the controllable switches such that in response to the control lines being activated in the predetermined sequence, each of the analog storage lines is coupled in turn to each of the analog signal lines in a sequence having a predetermined rotating order, wherein the predetermined rotating order is identical for each of the analog storage lines, except that the sequence corresponding to each of the analog storage lines begins with a different one of the analog signal lines, wherein the discrete-time phase locked loop further comprises a controlled oscillator coupled to the output node of the discrete-time analog computing element for producing the generated signal.

Claim 18

A communication receiver, comprising: an antenna for intercepting a signal including information; a receiver element coupled to the antenna for demodulating the signal to derive the information; a processor coupled to the receiver element for processing the information; a synthesizer coupled to the processor for producing a generated signal utilized by the communication receiver, the synthesizer comprising: a reference oscillator for generating a reference signal; and a discrete-time phase locked loop, comprising: a phase error detector having a discrete-time pulse width modulation (DTPWM) output signal, the phase error detector coupled to the reference oscillator for receiving the reference signal and coupled to the generated signal for detecting a phase difference between the reference signal and the generated signal; and a discrete-time analog computing element, comprising: an input node coupled to the phase error detector and coupled to at least one discrete-time analog queuing element for receiving the DTPWM output signal; an output node coupled to the at least one discrete-time analog queuing element for providing a computed output signal responsive to the DTPWM output signal of the phase error detector; a clock and logic circuit coupled to the at least one discrete-time analog queuing element for generating a plurality of control signals activated in a predetermined sequence; and the at least one discrete-time analog queuing element, comprising: N analog signal lines, wherein N is a positive integer; N analog storage lines; N 2 controllable switches, each controllable switch of the N 2 controllable switches coupled between each of the N analog signal lines and each of the N analog storage lines; N charge storage elements, each charge storage element of the N charge storage elements coupled between each of the N analog storage lines and a common circuit node; and N control lines, each control line coupled to N of the N 2 controllable switches and coupled to the clock and logic circuit, the N control lines for controlling the controllable switches such that in response to the control lines being activated in the predetermined sequence, each of the analog storage lines is coupled in turn to each of the analog signal lines in a sequence having a predetermined rotating order, wherein the predetermined rotating order is identical for each of the analog storage lines, except that the sequence corresponding to each of the analog storage lines begins with a different one of the analog signal lines, wherein the discrete-time phase locked loop further comprises a controlled oscillator coupled to the output node of the discrete-time analog computing element for producing the generated signal.

Claim 19

The communication receiver of claim 14, wherein an analog signal line of the N analog signal lines is coupled to a reference circuit node for setting a predetermined charge and resultant voltage on a charge storage element of the N charge storage elements in response to the analog signal line being coupled to the charge storage element through one of the N 2 controllable switches, and wherein at least one of the analog signal lines is an input for receiving at least one discrete-time analog input signal, and wherein at least one of the analog signal lines is an output for delivering at least one discrete-time output signal.

Claim 20

The communication receiver of claim 14, wherein the at least one discrete-time analog queuing element further comprises at least one charge transfer circuit, comprising: an input for receiving an input voltage change; and an output coupled to one of the analog signal lines for delivering thereto a charge proportional to the input voltage change.

Claim 21

The communication receiver of claim 14, wherein the at least one discrete-time analog queuing element further comprises at least one charge transfer circuit, comprising: an input coupled to one of the analog signal lines for receiving therefrom an input voltage change; and an output for providing a charge proportional to the input voltage change.

Claim 22

The communication receiver of claim 14, wherein the controlled oscillator produces a desired signal operating at a desired frequency, and wherein the controlled oscillator comprises a frequency divider coupled to the desired signal for frequency dividing the desired signal to produce the generated signal.