Phase-loched loop circuits and voltage controlled oscillator circuits

Claim 2

A voltage controlled oscillator comprising: (a) an oscillating circuit having two control inputs and means for outputting an oscillator output signal, said oscillating circuit being adapted to generate said oscillator output signal at a frequency dependent on a difference between voltages applied to said control inputs; and (b) an input control circuit comprising first input means for providing a first control input signal of a first polarity to one of said two control inputs and second input means for providing a second control input signal of a second polarity opposite to said first polarity to the other one of said two control inputs.

Claim 3

A voltage controlled oscillator circuit as claimed in claim 1, wherein said input control circuit comprises (a) a first input buffer circuit having a first input for receiving a first control voltage and a first output connected to one said control input of said oscillating circuit, said first input buffer circuit including a buffer amplifier and an inductor connected between said first input and said first output, and (b) a second input buffer circuit having a second input for receiving a second control voltage and a second output connected to the other said control input of said oscillating circuit, said second input buffer circuit including a buffer amplifier and an inductor connected between said second input and said second output.

Claim 4

A voltage controlled oscillator circuit as claimed in claim 1, wherein said voltage controlled oscillator and said input control circuit are provided on an integrated VCO module.

Claim 5

A voltage controlled oscillator circuit comprising: (a) a voltage controlled oscillator having a control input for applying a control signal to said oscillator and an output for providing an output signal having an output frequency varying in response to the applied control signal; (b) a buffering circuit having an input connected to the output of said oscillator, a first and second output, said buffer circuit being adapted to conduct the output signal from said oscillator to said first and second outputs and to isolate said first output from external signals applied to said second output, said oscillator and said buffer circuit being provided on an integrated VCO module, and wherein said buffering circuit includes a power divider.

Claim 6

A voltage controlled oscillator circuit comprising: (a) a voltage controlled oscillator having a control input for applying a control signal to said oscillator and an output for providing an output signal having an output frequency varying in response to the applied control signal; (b) a buffering circuit having an input connected to the output of said oscillator, a first and second output, said buffer circuit being adapted to conduct the output signal from said oscillator to said first and second outputs and to isolate said first output from external signals applied to said second output, said oscillator and said buffer circuit being provided on an integrated VCO module, and wherein said buffering circuit includes a power divider.

Claim 7

A voltage controlled oscillator circuit as claimed in claim 4, wherein said power divider comprises a passive power divider.

Claim 8

A voltage controlled oscillator circuit as claimed in claim 4, wherein said power divider comprises a active power divider.

Claim 9

A voltage controlled oscillator circuit as claimed in claim 4, wherein said buffering circuit further includes a high frequency amplifier.

Claim 10

A voltage controlled oscillator circuit comprising: (a) a voltage controlled oscillator having a control input for applying a control signal to said oscillator and an output for providing an output signal having an output frequency varying in response to the applied control signal; (b) a buffering circuit having an input connected to the output of said oscillator, a first and second output, said buffer circuit being adapted to conduct the output signal from said oscillator to said first and second outputs and to isolate said first output from external signals applied to said second output, said oscillator and said buffer circuit being provided on an integrated VCO module, and wherein said buffering circuit includes a hybrid.

Claim 11

A voltage controlled oscillator circuit comprising: (a) a voltage controlled oscillator having a control input for applying a control signal to said oscillator and an output for providing an output signal having an output frequency varying in response to the applied control signal; (b) a buffering circuit having an input connected to the output of said oscillator, a first and second output, said buffer circuit being adapted to conduct the output signal from said oscillator to said first and second outputs and to isolate said first output from external signals applied to said second output, said oscillator and said buffer circuit being provided on an integrated VCO module, and wherein said buffering circuit includes a hybrid.

Claim 12

A voltage controlled oscillator circuit as claimed in claim 8, wherein said hybrid is a 90 degree hybrid.

Claim 13

A voltage controlled oscillator circuit as claimed in claim 8, wherein said hybrid is a 180 degree hybrid.

Claim 14

A voltage controlled oscillator circuit as claimed in claim 8, wherein said buffering circuit further includes a high frequency amplifier.

Claim 15

A phase-locked loop circuit comprising: (a) a phase detector having a first input for receiving a reference signal, a second input for receiving a comparison signal, and an output for providing a control signal having a control frequency; (b) a voltage controlled oscillator having a control input connected to said output of said phase detector for applying said control signal to said oscillator and an output for providing an output signal having an output frequency varying in response to the applied control signal; (c) a buffering circuit having an input connected to the output of said oscillator, a first and second output, said buffer circuit being adapted to conduct the output signal from said oscillator to said first and second outputs and to isolate said first output from external signals applied to said second output, said buffer circuit and said oscillator being provided on an integrated VCO module; and (d) a digital interface circuit having an input connected to said second output of said buffer circuit and an output connected to said second input of said phase detector for providing an output signal having a comparison frequency to said phase detector for comparison with the reference signal to generate said control signal, wherein said buffering circuit comprises a power-divider.

Claim 16

A phase-locked loop circuit comprising: (a) a phase detector having a first input for receiving a reference signal, a second input for receiving a comparison signal, and an output for providing a control signal having a control frequency; (b) a voltage controlled oscillator having a control input connected to said output of said phase detector for applying said control signal to said oscillator and an output for providing an output signal having an output frequency varying in response to the applied control signal; (c) a buffering circuit having an input connected to the output of said oscillator, a first and second output, said buffer circuit being adapted to conduct the output signal from said oscillator to said first and second outputs and to isolate said first output from external signals applied to said second output, said buffer circuit and said oscillator being provided on an integrated VCO module; and (d) a digital interface circuit having an input connected to said second output of said buffer circuit and an output connected to said second input of said phase detector for providing an output signal having a comparison frequency to said phase detector for comparison with the reference signal to generate said control signal, wherein said buffering circuit comprises a power-divider.

Claim 17

A phase-locked loop circuit as claimed in claim 12, wherein said power divider comprises a passive power divider.

Claim 18

A phase-locked loop circuit as claimed in claim 12, wherein said power divider comprises an active power divider.

Claim 19

A phase-locked loop circuit as claimed in claim 12, wherein said buffering circuit further includes a high frequency amplifier.

Claim 20

A phase-locked loop circuit comprising: (a) a phase detector having a first input for receiving a reference signal, a second input for receiving a comparison signal, and an output for providing a control signal having a control frequency; (b) a voltage controlled oscillator having a control input connected to said output of said phase detector for applying said control signal to said oscillator and output for providing an output signal having an output frequency varying in response to the applied control signal; (c) a buffering circuit having an input connected to the output of said oscillator, a first and second output, said buffer circuit being adapted to conduct the output signal from said oscillator to said first and second outputs and to isolate said first output from external signals applied to said second output, said buffer circuit and said oscillator being provided on an integrated VCO module; and (d) a digital interface circuit having an input connected to said second output of said buffer circuit and an output connected to said second input of said phase detector for comparison frequency to said phase detector for comparison with the reference signal to generate said control signal, wherein said buffering circuit includes a hybrid.

Claim 21

A phase-locked loop circuit comprising: (a) a phase detector having a first input for receiving a reference signal, a second input for receiving a comparison signal, and an output for providing a control signal having a control frequency; (b) a voltage controlled oscillator having a control input connected to said output of said phase detector for applying said control signal to said oscillator and output for providing an output signal having an output frequency varying in response to the applied control signal; (c) a buffering circuit having an input connected to the output of said oscillator, a first and second output, said buffer circuit being adapted to conduct the output signal from said oscillator to said first and second outputs and to isolate said first output from external signals applied to said second output, said buffer circuit and said oscillator being provided on an integrated VCO module; and (d) a digital interface circuit having an input connected to said second output of said buffer circuit and an output connected to said second input of said phase detector for comparison frequency to said phase detector for comparison with the reference signal to generate said control signal, wherein said buffering circuit includes a hybrid.

Claim 22

A phase-locked loop circuit as claimed in claim 16, wherein said buffering circuit further includes a high frequency amplifier.

Claim 23

A phase-locked loop circuit comprising: (a) a phase detector having a first input for receiving a reference signal, a second input for receiving a comparison signal, an output for providing a control signal having a control frequency, an analog ground and a digital ground; (b) a voltage controlled oscillator having a control input connected to said output of said phase detector for applying said control signal to said oscillator, an output for providing an output signal having an output frequency varying in response to the applied control signal, and an analog ground; (c) a digital interface circuit having an input connected to said output of said oscillator, an output connected to said second input of said phase detector for providing an output signal having a comparison frequency to said phase detector for comparison with the reference signal to generate said control signal, an analog ground and a digital ground; and (d) grounding means for connecting each said analog ground of the phase-locked loop circuit to a common analog ground and each said digital ground of the phase-locked loop circuit to a common digital ground separate from said common analog ground.

Claim 24

A phase-locked loop circuit comprising: (a) a phase detector having a first input for receiving a reference signal, a second input for receiving a comparison signal, an output for providing a control signal having a control frequency, an analog ground and a digital ground; (b) a voltage controlled oscillator having a control input connected to said output of said phase detector for applying said control signal to said oscillator, an output for providing an output signal having an output frequency varying in response to the applied control signal, and an analog ground; (c) a digital interface circuit having an input connected to said output of said oscillator, an output connected to said second input of said phase detector for providing an output signal having a comparison frequency to said phase detector for comparison with the reference signal to generate said control signal, an analog ground and a digital ground; and (d) grounding means for connecting each said analog ground of the phase-locked loop circuit to a common analog ground and each said digital ground of the phase-locked loop circuit to a common digital ground separate from said common analog ground.

Claim 25

A phase-locked loop circuit as claimed in claim 18, further comprising a buffer circuit having an input connected to the output of said oscillator, a first output, a second output connected to said input of said control circuit, said buffer circuit being adapted to conduct the output signal from said oscillator to said first and second outputs and to isolate said first output from external signals applied to said second output, and an analog ground connected to said common analog ground.

Claim 26

A phase-locked loop circuit as claimed in claim 19, further comprising a low pass filter circuit connected between said output of said phase detector and said input of said oscillator, said low pass filter comprising an analog ground connected to said common analog ground.

Claim 27

A phase-locked loop circuit comprising: (a) a phase detector having a first input for receiving a reference signal, a second input for receiving a comparison signal, an output for providing a primary control signal having a control frequency, an analog ground and a digital ground; (b) a conditioning circuit having a first input connected to said output of said phase detector, a first output for providing a first control signal based on the primary control signal and a second output for providing a second control signal based on the primary control signal, said first and second control signals having opposite polarities; (c) a voltage controlled oscillator having two control inputs connected to said first and second outputs of said conditioning circuit, an input control circuit for applying the first and second control signals to said control inputs of said oscillator, a supply input for providing a supply voltage signal to said oscillator, an output for providing an output signal having an output frequency varying in response to the applied control signals, and an analog ground; (d) a voltage regulator for providing a regulated voltage to said supply input to reduce spurious response of the output signal, said voltage controlled oscillator and said voltage regulator being provided on an integrated VCO module; (e) frequency multiplication means for increasing the output frequency of the output signal; (e) a buffer circuit having an input connected to the output of said oscillator, a first and second output, said buffer circuit being adapted to conduct the output signal from said oscillator to said first and second outputs and to isolate said first output from external signals applied to said second output, and an analog ground; (g) a digital interface circuit having an input connected to said second output of said buffer circuit, an output connected to said second input of said phase detector for providing an output signal having a comparison frequency to said phase detector for comparison with the reference signal to generate said control signal, an analog ground and a digital ground; and (h) grounding means for connecting each said analog ground of the phase-locked loop circuit to a common analog ground and each said digital ground of the phase-locked loop circuit to a common digital ground separate from said common analog ground.

Claim 28

A phase-locked loop circuit comprising: (a) a phase detector having a first input for receiving a reference signal, a second input for receiving a comparison signal, an output for providing a primary control signal having a control frequency, an analog ground and a digital ground; (b) a conditioning circuit having a first input connected to said output of said phase detector, a first output for providing a first control signal based on the primary control signal and a second output for providing a second control signal based on the primary control signal, said first and second control signals having opposite polarities; (c) a voltage controlled oscillator having two control inputs connected to said first and second outputs of said conditioning circuit, an input control circuit for applying the first and second control signals to said control inputs of said oscillator, a supply input for providing a supply voltage signal to said oscillator, an output for providing an output signal having an output frequency varying in response to the applied control signals, and an analog ground; (d) a voltage regulator for providing a regulated voltage to said supply input to reduce spurious response of the output signal, said voltage controlled oscillator and said voltage regulator being provided on an integrated VCO module; (e) frequency multiplication means for increasing the output frequency of the output signal; (e) a buffer circuit having an input connected to the output of said oscillator, a first and second output, said buffer circuit being adapted to conduct the output signal from said oscillator to said first and second outputs and to isolate said first output from external signals applied to said second output, and an analog ground; (g) a digital interface circuit having an input connected to said second output of said buffer circuit, an output connected to said second input of said phase detector for providing an output signal having a comparison frequency to said phase detector for comparison with the reference signal to generate said control signal, an analog ground and a digital ground; and (h) grounding means for connecting each said analog ground of the phase-locked loop circuit to a common analog ground and each said digital ground of the phase-locked loop circuit to a common digital ground separate from said common analog ground.

Claim 29

A voltage controlled oscillator comprising: (a) an oscillating circuit having two control inputs, said oscillating circuit being adapted to oscillate at a frequency dependent on a difference between voltages applied to said control inputs; and (b) an input control circuit for applying control input signals of opposite, polarity to said control inputs, said input control circuit comprising (i) a first input buffer circuit having a first input for receiving a first control voltage and a first output connected to one said control input of said oscillating circuit, said first input buffer circuit including a buffer amplifier and an inductor connected between said first input and said first output, and (ii) a second input buffer circuit having a second input for receiving a second control voltage and a second output connected to the other said control input of said oscillating circuit, said second input buffer circuit including a buffer amplifier and an inductor connected between said second input and said second output.

Claim 30

A voltage controlled oscillator comprising: (a) an oscillating circuit having two control inputs, said oscillating circuit being adapted to oscillate at a frequency dependent on a difference between voltages applied to said control inputs; and (b) an input control circuit for applying control input signals of opposite, polarity to said control inputs, said input control circuit comprising (i) a first input buffer circuit having a first input for receiving a first control voltage and a first output connected to one said control input of said oscillating circuit, said first input buffer circuit including a buffer amplifier and an inductor connected between said first input and said first output, and (ii) a second input buffer circuit having a second input for receiving a second control voltage and a second output connected to the other said control input of said oscillating circuit, said second input buffer circuit including a buffer amplifier and an inductor connected between said second input and said second output.