Mapping calculation units by dividing a calculation model which can be calculated in parallel on an application program

Claim 3

A method of mapping a calculation model in a parallel computer as claimed in claim 1, wherein a total sum L of interprocessor distances is used as a communication cost evaluation function, and said mapping step c) being carried out so that the total sum L is minimized.

Claim 4

A method of mapping a calculation model in a parallel computer as claimed in claim 2, wherein, when adjacent lattice points Pi and Pj of the calculation units are mapped into particular points (Xi, Yi) and (Xj, Yj) on a two-dimensional lattice pattern, a distance Iij between Pi and Pj being represented by: lij=|Xi-Xj|+|Yi-Yj|, the evaluation function being represented by L=Σlij, optimum mapping being obtained when the evaluation function has a minimum value.

Claim 5

A method of mapping a calculation model in a parallel computer as claimed in claim 2, further comprising the steps of: e) changing a mapping position after determining an initial mapping position: f) calculating a variation of length ΔL; g) adopting a change of the mapping position when ΔL<0; h) extracting a random number X (0<X 1) when ΔL<0 does not hold and calculating exp(-ΔL/T), T being a parameter or a standard in determining a probability; i) not adopting the change of the mapping position when exp(-ΔL/T)<X; j) adopting the change of the mapping position when exp(-ΔL/T)<X does not hold; and k) repeating processing from steps e) to j) with T reduced.

Claim 6

A method of mapping a calculation model in a parallel computer as claimed in claim 4, wherein processing is carried out in a parallel fashion.

Claim 7

A method of mapping a calculation model in a parallel computer as claimed in claim 1, wherein said mapping step c) includes the substeps of: i) spatially dividing a three-dimensional calculation model into calculation units in three directions X, Y, and Z; ii) mapping the calculation units into processors in a two-dimensional array; iii) dividing the three-dimensional calculation model into a plurality of calculation units, n in number, in a ZX plane; iv) arranging the calculation units in the direction Y adjacent in square in the two-dimensional array; and v) arranging the calculation units in direction Z and X at every second position.

Claim 8

A method of mapping a calculation model in a parallel computer as claimed in claim 6, further comprising the steps of: vi) defining in the three-dimensional calculation model, the calculation units in directions X, Y, and Z as VCX, VCY, and VCZ, respectively, while defining numbers of division in the directions X, Y, and Z as VX, VY, and VZ, respectively; vii) mapping the two-dimensional array; viii) defining numbers of X-directional processors and Y-directional processors as PCX and PCY, respectively; ix) defining numbers of division in the directions X and Y as PX and PY, respectively; x) dividing the processors into groups; xi) dividing the three-dimensional calculation model by VX=PCX/2, VY=PCY/2, and YZ=0 to form rectangular units called main units, each main unit being assigned with a serial number (main unit number); xii) further dividing the main unit into four in the direction Z to form resultant units called subunits, each subunit being assigned a serial number (subunit number); xiii) dividing the two-dimensional array, the processors being divided by PX=PCX/2 and PY=PCY/2 into groups, each group being assigned a serial number (group number); iv) scattering and mapping subunit numbers 0 to 3 into the group of physical processors having a group number similar to a main unit number of the three-dimensional model so that 0 and 1, 1 and 2, 2 and 3, 3 and 0 are respectively adjacent.

Claim 9

A method of mapping a calculation model in a parallel computer as claimed in claim 1, wherein said mapping step c) comprises the substeps of: i) spatially dividing a three-dimensional calculation model into calculation units in three directions X, Y, and Z; ii) mapping the calculation units into processors in a two-dimensional array; iii) dividing the three-dimensional calculation model into a plurality of calculation units, n in number, in a ZX plane; and iv) sequentially arranging the calculation units in the two-dimensional array so that the calculation units in directions Z and X are arranged adjacent while the calculation units in the direction Y are regularly arranged.

Claim 10

A method of mapping a calculation model in a parallel computer as claimed in claim 8, wherein said substep iv) comprises, in the three-dimensional calculation model; aa) defining the calculation units in directions X, Y, and Z as VCX, VCY, and VCZ, respectively, while numbers of division in the directions X, Y, and Z are defined as VX, VY, and VZ, respectively; bb) dividing the three-dimensional calculation model by VX=0, VY=0, and YZ=VCZ to form rectangular units called main Units, each main unit being assigned a serial main unit number, numbers of the X-directional and the Y-directional calculation units of the main unit being represented by vx and vy, respectively; said substep ii) comprises, in the two-dimensional array subjected to mapping; aa) defining numbers of X-directional processors and Y-directional processors as PCX and PCY, respectively; bb) defining numbers of division in directions X and Y as PX and PY, respectively; and cc) dividing the processors into groups; dd) dividing processors by PX=PCX/vx and PY=PCY/vy into groups, each group being assigned a serial group number; ee) sequentially arranging the main units along the direction X of the two-dimensional array in the order of the serial group numbers corresponding to a position represented by vx=PX and vy=PY and shifting an arrangement along the direction Y when reaching the processor at one end in the direction X; and ff) sequentially arranging the main units reversely in the direction X in an order of serial group numbers, shifting an arrangement again in the direction Y when reaching the processor at an opposite end in the direction X, and repeating mapping in a zigzag fashion.

Claim 11

A method of mapping a calculation model in a parallel computer as claimed in claim 1, said step c) further comprises the substeps of: i) storing, in a database, optimum mapping patterns obtained by said mapping step c); and ii) selecting a particular optimum mapping pattern adapted to a particular calculation model with reference to the database to carry out parallel processing.

Claim 12

A communication library program for use in a parallel computer, the parallel computer including a plurality of processors for implementing processing in a parallel fashion by transferring data and information among the processors from one to another through communication means, the communication library program being used in implementing parallel processing by the plurality of processors to calculate an N-dimensional calculation model to be executed and processed at a user's demand, said communication library program comprising: a dividing routine for dividing said N-dimensional calculation model into a plurality of calculation units each having an identification code; a supervising routine for establishing an address conversion table that indicates the location of the processors assigned to said calculation units; and a mapping routine for desiredly mapping said calculation units into the plurality of processors, through an address conversion table, and implementing interprocessor communication by the identification codes assigned to the calculation units.

Claim 13

A communication library program for use in a parallel computer, the parallel computer including a plurality of processors for implementing processing in a parallel fashion by transferring data and information among the processors from one to another through communication means, the communication library program being used in implementing parallel processing by the plurality of processors to calculate an N-dimensional calculation model to be executed and processed at a user's demand, said communication library program comprising: a dividing routine for dividing said N-dimensional calculation model into a plurality of calculation units each having an identification code; a supervising routine for establishing an address conversion table that indicates the location of the processors assigned to said calculation units; and a mapping routine for desiredly mapping said calculation units into the plurality of processors, through an address conversion table, and implementing interprocessor communication by the identification codes assigned to the calculation units.

Claim 14

A communication library program for use in a parallel computer as claimed in claim 11, wherein a total sum L of interprocessor distances is used as a communication cost evaluation function in said mapping routine, said mapping being carried out so that said total sum L is minimized.

Claim 15

A communication library program for use in a parallel computer as claimed in claim 12, wherein, when adjacent lattice points PI and Pj of said calculation units are mapped into particular points (Xi, Yi) and (Xj, Yj) on a two-dimensional lattice pattern, the distance IiJ between Pi and Pj is represented by: lij=|Xi-Xj|+|Yi-Yj|, said evaluation function being represented by L=Σlij, optimum mapping being obtained when said evaluation function has a minimum value.

Claim 16

A communication library program for use in a parallel computer as claimed in claim 12, comprising the steps of: a) changing a mapping position after determining an initial mapping position; b) calculating a variation of length (variation of said total sum of the distances) ΔL; c) adopting the change of the mapping position when ΔL<0; d) extracting a random number X (0<X<1) when ΔL<0 does not hold and calculating exp(-ΔL/T) (T being a parameter or a standard in determining a probability); e) not adopting the change of the mapping position when exp(-ΔL/T) X; f) adopting the change of the mapping position when exp (-ΔL/T)<X does not hold; and g) repeating processing of steps (a) to (f) with T reduced.

Claim 17

A communication library program for use in a parallel computer as claimed in claim 14, wherein processing is carried out in a parallel fashion.

Claim 18

A communication library program for use in a parallel computer as claimed in claim 11, said mapping being such that a three-dimensional calculation model is spatially divided into calculation units in three directions X, Y, and Z and said calculation units are mapped into processors in a two-dimensional array, wherein: said three-dimensional calculation model is divided into a plurality of calculation units, n in number, in a ZX plane, the calculation units in the direction Y being arranged adjacent in square in said two-dimensional array, said calculation units in directions Z and X being arranged at every second positions.

Claim 19

A communication library program for us in a parallel computer as claimed in claim 16, wherein: in said three-dimensional calculation model, said calculation units in directions X, Y, and Z are defined as VCX, VCY, and VCZ, respectively, while numbers of division in the directions X, Y, and Z are defined as VX, VY, and VZ, respectively; in said two-dimensional array subjected to mapping, numbers of X-directional processors and Y-directional processors being defined as PCX and PCY, respectively, the numbers of division in the directions X and Y being defined as PX and PY, respectively, said processors being divided into groups; said three-dimensional calculation model being divided by VX=PCX/2, VY=PCY/2, and YZ=0 to form rectangular units called main units, each main unit being assigned with a serial said main unit being further divided into four in the direction Z to form resultant units called subunits, each subunit being assigned a serial number (subunit number); in said two-dimensional array, said processors being divided by PX=PCX/2 and PY=PCY/2 into groups, each group being assigned a serial; and subunit numbers 0 to 3 being scattered and mapped into said processors having the group number similar to the main unit number of said three-dimensional model so that 0 and 1, 1 and 2, 2 and 3, 3 and 0 are respectively adjacent.

Claim 20

A communication library program for use in a parallel computer as claimed in claim 11, said mapping being such that a three-dimensional calculation model is spatially divided into calculation units in three directions X, Y, and Z and said calculation units are mapped into processors in a two-dimensional array, wherein: said three-dimensional calculation model is divided into a plurality of calculation units, n in number, in a ZX plane, said calculation units being sequentially arranged in said two-dimensional array so that said calculation units in the directions Z and X are arranged while said calculation units in the direction Y are regularly arranged (spaced at a distance corresponding to n units).

Claim 21

A communication library program for use in a parallel computer as claimed in claim 18, wherein: in said three-dimensional calculation model, calculation units in directions X, Y, and Z are defined as VCX, VCY, and VCZ, respectively, while numbers of division in the directions X, Y, and Z are defined as VX, VY, and VZ, respectively; in a two-dimensional array subjected to mapping, numbers of X-directional processors and Y-directional processors being defined as PCX and PCY, respectively, numbers of division in the directions X and Y being defined as PX and PY, respectively, said processors being divided into groups; said three-dimensional calculation model being divided by VX=0, VY=0, and YZ=VCZ to form rectangular units called main units, each main unit being assigned a serial, numbers of the X-directional and the Y-directional calculation units of said main unit being represented by vx and vy, respectively; in said two-dimensional array, said processors being divided by PX=PXC/vx and PY=PCY/vy into groups, each group being assigned a serial; corresponding to a position represented by vx=PX and vy=PY, said main units being sequentially arranged along the direction X of said two-dimensional array in an order of the group numbers, an arrangement being shifted along the direction Y when reaching the processor at one end in the direction X, said main units being sequentially arranged reversely in the direction X in an order of the serial main unit numbers, an arrangement being shifted again in the direction Y when reaching the processor at an opposite end in the direction X, mapping being thereafter repeated in a zigzag fashion.

Claim 22

A communication library program for use in a parallel computer as claimed in claim 11, wherein optimum mapping patterns obtained by said mapping are stored in a database, a particular optimum mapping pattern adapted to a particular calculation model being selected with reference to said database to carry out parallel processing.

Claim 23

A parallel computer including a plurality of processors for implementing parallel processing by transferring data and information among said processors from one to another through communication means to calculate an N-dimensional calculation model to be executed and processed at a user's demand, said parallel computer comprising: a calculation model dividing section for dividing an N-dimensional calculation model into a plurality of calculation units each having an identification code; a supervising section for establishing an address conversion table that indicates the location of the processors assigned to said calculation units; and a mapping section for desiredly mapping said calculation units into said processors through an address conversion table, interprocessor communication being carried out by the identification codes assigned to said calculation units.

Claim 24

A parallel computer including a plurality of processors for implementing parallel processing by transferring data and information among said processors from one to another through communication means to calculate an N-dimensional calculation model to be executed and processed at a user's demand, said parallel computer comprising: a calculation model dividing section for dividing an N-dimensional calculation model into a plurality of calculation units each having an identification code; a supervising section for establishing an address conversion table that indicates the location of the processors assigned to said calculation units; and a mapping section for desiredly mapping said calculation units into said processors through an address conversion table, interprocessor communication being carried out by the identification codes assigned to said calculation units.

Claim 25

A parallel computer as claimed in claim 21, wherein said mapping section comprises an interprocessor distance calculating unit for calculating a total sum L of interprocessor distances as a communication cost evaluation function, optimum mapping being obtained when said total sum L has a minimum value.

Claim 26

A parallel computer as claimed in claim 22, wherein said mapping section comprises a judging unit for judging whether or not the total sum L obtained by said interprocessor distance calculating unit has a minimum value, optimum mapping being obtained when the total sum L has a minimum value.

Claim 27

A parallel computer as claimed in claim 22, which changes a mapping position after determining an initial mapping position, calculates a variation of length ΔL, adopts the change of said mapping position when ΔL<0, extracts a random number X (0<X<1) when ΔL<0 does not hold, calculates exp(-ΔL/T) (T being a parameter or a standard in determining a probability), does not adopt the change of said mapping position when exp(-ΔL/T)<X, adopts the change of said mapping position when exp(-ΔL/T)<X does not hold, and repeats processing from with T reduced.

Claim 28

A parallel computer as claimed in claim 24, wherein processing is carried out in a parallel fashion.

Claim 29

A parallel computer as claimed in claim 21, wherein, when adjacent lattice points Pi and Pj of said calculation units are mapped into particular points (Xi, Yi) and (Xj, Yj) on a two-dimensional lattice pattern, a distance Iij between Pi and Pj is represented by: lij=|Xi-Xj|+|Yi-Yj|, said evaluation function being represented by L=Σlij, optimum mapping being obtained when said evaluation function has a minimum value.

Claim 30

A parallel computer as claimed in claim 21, wherein said mapping section being operable so that a three-dimensional calculation model is spatially divided into calculation units in three directions X, Y, and Z and said calculation units are mapped into processors in a two-dimensional array, wherein: said three-dimensional calculation model is divided into a plurality of calculation units, n in number, in a ZX plane, the calculation units in the direction Y being arranged adjacent in square in said two-dimensional processor array, the calculation units in directions Z and X being arranged at every second position.

Claim 31

A parallel computer as claimed in claim 27, wherein: in said three-dimensional calculation model, said calculation units in directions X, Y, and Z are defined as VCX, VCY, and VCZ, respectively, while numbers of division in the directions X, Y, and Z are defined as VX, VY, and VZ, respectively; in a two-dimensional processor array subjected to mapping, numbers of X-directional processors and Y-directional processors being defined as PCX and PCY, respectively, numbers of division in the directions X and Y being defined as PX and PY, respectively, said processors being divided into groups; said three-dimensional calculation model being divided by VX=PCX/2, VY=PCY/2, and YZ=0 to form rectangular units called main units, each main unit being assigned with a serial, said main unit being further divided into four in the direction Z to form resultant units called subunits, each subunit being assigned with a serial; in said two-dimensional array, said processors being divided by PX=PCX/2 and PY=PCY/2 into groups, each group being assigned with a serial; subunit numbers 0 to 3 being scattered and mapped into the group of said physical processors having the group number similar to the main unit number of said three-dimensional model so that 0 and 1, 1 and 2, 2 and 3, 3 and 0 are respectively adjacent.

Claim 32

A parallel computer as claimed in claim 21, said mapping section being operable so that a three-dimensional calculation model is spatially divided into calculation units in three directions X, Y, and Z and said calculation units are mapped into processors in a two-dimensional array, wherein: said three-dimensional calculation model is divided into a plurality of calculation units, n in number, in a ZX plane, said calculation units being sequentially arranged in said two-dimensional array so that the calculation units in directions Z and X are arranged adjacent while the calculation units in the direction Y are regularly arranged (spaced at a distance corresponding to n units).

Claim 33

A parallel computer as claimed in claim 29, wherein: in said three-dimensional calculation model, calculation units in directions X, Y, and Z are defined as VCX, VCY, and VCZ, respectively, while numbers of division in the directions X, Y, and Z are defined as VX, VY, and VZ, respectively; in a two-dimensional array subjected to mapping, numbers of X-directional processors and Y-directional processors being defined as PCX and PCY, respectively, numbers of division in the directions X and Y being defined as PX and PY, respectively, said processors being divided into groups; said three-dimensional calculation model being divided by VX=0, VY=0 and YZ=VCZ to form rectangular units called main units, each main unit being assigned with a serial, numbers of the X-directional and the Y-directional calculation units of said main unit being represented by vx and vy, respectively; in said two-dimensional processor array, said processors being divided by PX=PCX/vx and PY=PCY/vy into groups, each group being assigned with a serial; corresponding to a position represented by vx=PX and vy=PY, said main units being sequentially arranged along the direction X of said two-dimensional array in an order of the serial main unit numbers, an arrangement being shifted along the direction Y when reaching the processor at one end in the direction X, said main units being then sequentially arranged reversely in the direction X in an order of the serial main unit numbers, an arrangement being shifted again in the direction Y when reaching the processor at an opposite end in the direction X, mapping being thereafter repeated in a zigzag fashion.

Claim 34

A parallel computer as claimed in claim 21, further comprising a database section, optimum mapping patterns obtained by said mapping being stored in said database section, a particular optimum mapping pattern adapted to a particular calculation model being selected with reference to said database section to carry out parallel processing.