US5649010A
Expired / Lapsed
US
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Send filter for an echo canceler
Assignee: Siemens Schweiz AG
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Filing: 1995-07-19
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Granted: 1997-07-15
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Expires: 2015-07-19
Abstract
Abstract Send filter for an echo canceler. A circuit includes a send path carrying a send signal, a receiver path carrying a received signal, an adaptive filter, a compensator contained in the received path, a digital/analog converter, a transmission unit, and a transmission line attached to the transmission unit, wherein over the transmission line, at least the send signal, the received signal, the echo signal portions are transmitted, and the send and received path are additionally connected with the transmission unit and the send signal is transmitted to the adaptive filter for the estimation of the echo signal which is processed in the compensator for the production of the receiving signal, with the send signal being conveyed, on the send path, to digital/analog converter, which, with the symbol rate of the send signal, produces square pulses, which in turn are transformed, in the send filter, connected with the digital/analog converter, into pulse forms useable for transmission via the transmission line, with the send filter being so conceived that the digital/analog converter merely has a resolution of two bits, whereby non-identities, particularly non-linearities, are compensated with the aid of the adaptive filter, the latter including at least one FIR filter portion of the storage compensation type.
Inventors
- 👤 Peter Gysel
- 👤 Bruno Wenger
- 👤 August Kaelin
- 👤 Daniel Mueller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:09
CPC Classifications
H; H04; H04B; H04B3/00; H04B3/02; H04B3/20; H04B3/23
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
202 words
A circuit arrangement comprised of: a send path carrying a send signal; a receiving path carrying a received signal; an adaptive filter; a compensator in the received path; a digital/analog converter; a transmission unit; and a transmission line attached to the transmission unit, wherein over the transmission line at least the send signal, the received signal and echo signal portions are transmitted, with the send path and the received path being connected with the transmission unit; with the send signal, for the estimation of the echo signal, being transmitted to the adaptive filter, wherein the estimated digital echo signal is transmitted to the compensator for the reduction of the echo signal portion in the received path, with the send signal being impressed upon the digital/analog converter and a send filter being interposed in the send path, between the digital/analog converter and the transmission unit, wherein the adaptive filter is comprised of at least an FIR (Finite Impulse Response) filter portion, with the FIR filter portion being of the storage compensation type, wherein the adaptive filter is additionally comprised of an IIR (Infinite Impulse Response) filter portion, and wherein the send filter has a transfer function T(s)=T 1 (s)*T 2 (s), wherein: ##EQU5##
Claim 2
Dependent Claim
202 words
A circuit arrangement comprised of: a send path carrying a send signal; a receiving path carrying a received signal; an adaptive filter; a compensator in the received path; a digital/analog converter; a transmission unit; and a transmission line attached to the transmission unit, wherein over the transmission line at least the send signal, the received signal and echo signal portions are transmitted, with the send path and the received path being connected with the transmission unit; with the send signal, for the estimation of the echo signal, being transmitted to the adaptive filter, wherein the estimated digital echo signal is transmitted to the compensator for the reduction of the echo signal portion in the received path, with the send signal being impressed upon the digital/analog converter and a send filter being interposed in the send path, between the digital/analog converter and the transmission unit, wherein the adaptive filter is comprised of at least an FIR (Finite Impulse Response) filter portion, with the FIR filter portion being of the storage compensation type, wherein the adaptive filter is additionally comprised of an IIR (Infinite Impulse Response) filter portion, and wherein the send filter has a transfer function T(s)=T 1 (s)*T 2 (s), wherein: ##EQU5##
Claim 3
Dependent Claim
25 words
The circuit arrangement of claim 1 wherein the conversion rate of the digital/analog converter is no greater than the symbol rate of the send signal.
Claim 4
Dependent Claim
282 words
A circuit arrangement comprised of: a send path carrying a send signal; a receiving path carrying a received signal; an adaptive filter; a compensator in the received path; a digital/analog converter; a transmission unit; and a transmission line attached to the transmission unit, wherein over the transmission line at least the send signal, the received signal and echo signal portions are transmitted, with the send path and the received path being connected with the transmission unit; with the send signal, for the estimation of the echo signal, being transmitted to the adaptive filter, wherein the estimated digital echo signal is transmitted to the compensator for the reduction of the echo signal portion in the received path, with the send signal being impressed upon the digital/analog converter and a send filter being interposed in the send path, between the digital/analog converter and the transmission unit, wherein the adaptive filter is comprised of at least an FIR (Finite Impulse Response) filter portion, with the FIR filter portion being of the storage compensation type, wherein in the FIR filter portion (FIR) at least one storage element and at least one digit delay element are provided, and when several digit delay elements are provided the several digit delay elements are switched in series with the first digit delay element being impressed with the send signal, wherein the send signal and the send signals delayed via the digit delay elements, are each impressed on at least one storage element, from each of which one value of one addressed storage cell in the storage element is read and accumulated in an adder, and wherein the send filter has a transfer function T(s)=T 1 (s)*T 2 (s), wherein: ##EQU6##
Claim 5
Dependent Claim
282 words
A circuit arrangement comprised of: a send path carrying a send signal; a receiving path carrying a received signal; an adaptive filter; a compensator in the received path; a digital/analog converter; a transmission unit; and a transmission line attached to the transmission unit, wherein over the transmission line at least the send signal, the received signal and echo signal portions are transmitted, with the send path and the received path being connected with the transmission unit; with the send signal, for the estimation of the echo signal, being transmitted to the adaptive filter, wherein the estimated digital echo signal is transmitted to the compensator for the reduction of the echo signal portion in the received path, with the send signal being impressed upon the digital/analog converter and a send filter being interposed in the send path, between the digital/analog converter and the transmission unit, wherein the adaptive filter is comprised of at least an FIR (Finite Impulse Response) filter portion, with the FIR filter portion being of the storage compensation type, wherein in the FIR filter portion (FIR) at least one storage element and at least one digit delay element are provided, and when several digit delay elements are provided the several digit delay elements are switched in series with the first digit delay element being impressed with the send signal, wherein the send signal and the send signals delayed via the digit delay elements, are each impressed on at least one storage element, from each of which one value of one addressed storage cell in the storage element is read and accumulated in an adder, and wherein the send filter has a transfer function T(s)=T 1 (s)*T 2 (s), wherein: ##EQU6##
Claim 6
Dependent Claim
270 words
A circuit arrangement comprised of: a send path carrying a send signal; a receiving path carrying a received signal; an adaptive filter; a compensator in the received path; a digital/analog converter; a transmission unit; and a transmission line attached to the transmission unit, wherein over the transmission line at least the send signal, the received signal and echo signal portions are transmitted, with the send path and the received path being connected with the transmission unit; with the send signal, for the estimation of the echo signal, being transmitted to the adaptive filter, wherein the estimated digital echo signal is transmitted to the compensator for the reduction of the echo signal portion in the received path, with the send signal being impressed upon the digital/analog converter and a send filter being interposed in the send path, between the digital/analog converter and the transmission unit, wherein the adaptive filter is comprised of at least an FIR (Finite Impulse Response) filter portion, with the FIR filter portion being of the storage compensation type, wherein in the FIR filter portion (FIR) at least one storage element and at least one digit delay element are provided, and when several digit delay elements are provided the several digit delay elements are switched in series with the first digit delay element being impressed with the send signal, wherein the send signal is tetravalent and the digital/analog converter has a resolution of two bits, whereby the FIR filter portion is so adaptively adjusted that non-idealities of the digital/analog converter are corrected, and wherein the send filter has a transfer function T(s)=T 1 (s)*T 2 (s), wherein: ##EQU7##
Claim 7
Dependent Claim
270 words
A circuit arrangement comprised of: a send path carrying a send signal; a receiving path carrying a received signal; an adaptive filter; a compensator in the received path; a digital/analog converter; a transmission unit; and a transmission line attached to the transmission unit, wherein over the transmission line at least the send signal, the received signal and echo signal portions are transmitted, with the send path and the received path being connected with the transmission unit; with the send signal, for the estimation of the echo signal, being transmitted to the adaptive filter, wherein the estimated digital echo signal is transmitted to the compensator for the reduction of the echo signal portion in the received path, with the send signal being impressed upon the digital/analog converter and a send filter being interposed in the send path, between the digital/analog converter and the transmission unit, wherein the adaptive filter is comprised of at least an FIR (Finite Impulse Response) filter portion, with the FIR filter portion being of the storage compensation type, wherein in the FIR filter portion (FIR) at least one storage element and at least one digit delay element are provided, and when several digit delay elements are provided the several digit delay elements are switched in series with the first digit delay element being impressed with the send signal, wherein the send signal is tetravalent and the digital/analog converter has a resolution of two bits, whereby the FIR filter portion is so adaptively adjusted that non-idealities of the digital/analog converter are corrected, and wherein the send filter has a transfer function T(s)=T 1 (s)*T 2 (s), wherein: ##EQU7##
Claim 8
Dependent Claim
277 words
A circuit arrangement comprised of: a send path carrying a send signal; a receiving path carrying a received signal; an adaptive filter; a compensator in the received path; a digital/analog converter; a transmission unit; and a transmission line attached to the transmission unit, wherein over the transmission line at least the send signal, the received signal and echo signal portions are transmitted, with the send path and the received path being connected with the transmission unit; with the send signal, for the estimation of the echo signal, being transmitted to the adaptive filter, wherein the estimated digital echo signal is transmitted to the compensator for the reduction of the echo signal portion in the received path, with the send signal being impressed upon the digital/analog converter and a send filter being interposed in the send path, between the digital/analog converter and the transmission unit, wherein the adaptive filter is comprised of at least an FIR (Finite Impulse Response) filter portion, with the FIR filter portion being of the storage compensation type, wherein in the FIR filter portion (FIR) at least one storage element and at least one digit delay element are provided, and when several digit delay elements are provided the several digit delay elements are switched in series with the first digit delay element being impressed with the send signal, wherein the send signal is tetravalent and the digital/analog converter has a resolution of two bits, whereby the FIR filter portion is so adaptively adjusted that non-idealities of the digital/analog converter are corrected, wherein the send signal is 2B1Q encoded, and wherein the send filter has a transfer function T(s)=T 1 (s)*T 2 (s), wherein: ##EQU8##
Claim 9
Dependent Claim
277 words
A circuit arrangement comprised of: a send path carrying a send signal; a receiving path carrying a received signal; an adaptive filter; a compensator in the received path; a digital/analog converter; a transmission unit; and a transmission line attached to the transmission unit, wherein over the transmission line at least the send signal, the received signal and echo signal portions are transmitted, with the send path and the received path being connected with the transmission unit; with the send signal, for the estimation of the echo signal, being transmitted to the adaptive filter, wherein the estimated digital echo signal is transmitted to the compensator for the reduction of the echo signal portion in the received path, with the send signal being impressed upon the digital/analog converter and a send filter being interposed in the send path, between the digital/analog converter and the transmission unit, wherein the adaptive filter is comprised of at least an FIR (Finite Impulse Response) filter portion, with the FIR filter portion being of the storage compensation type, wherein in the FIR filter portion (FIR) at least one storage element and at least one digit delay element are provided, and when several digit delay elements are provided the several digit delay elements are switched in series with the first digit delay element being impressed with the send signal, wherein the send signal is tetravalent and the digital/analog converter has a resolution of two bits, whereby the FIR filter portion is so adaptively adjusted that non-idealities of the digital/analog converter are corrected, wherein the send signal is 2B1Q encoded, and wherein the send filter has a transfer function T(s)=T 1 (s)*T 2 (s), wherein: ##EQU8##
Claim 10
Dependent Claim
252 words
A circuit arrangement comprised of: a send path carrying a send signal; a receiving path carrying a received signal; an adaptive filter; a compensator in the received path; a digital/analog converter; a transmission unit; and a transmission line attached to the transmission unit, wherein over the transmission line at least the send signal, the received signal and echo signal portions are transmitted, with the send path and the received path being connected with the transmission unit; with the send signal, for the estimation of the echo signal, being transmitted to the adaptive filter, wherein the estimated digital echo signal is transmitted to the compensator for the reduction of the echo signal portion in the received path, with the send signal being impressed upon the digital/analog converter and a send filter being interposed in the send path, between the digital/analog converter and the transmission unit, wherein the adaptive filter is comprised of at least an FIR (Finite Impulse Response) filter portion, with the FIR filter portion being of the storage compensation type, wherein in the FIR filter portion (FIR) at least one storage element and at least one digit delay element are provided, and when several digit delay elements are provided the several digit delay elements are switched in series with the first digit delay element being impressed with the send signal, wherein the adaptive filter is additionally comprised of an IIR (Infinite Impulse Response) filter portion, and wherein the send filter has a transfer function T(s)=T 1 (s)*T 2 (s), wherein: ##EQU9##
Claim 11
Dependent Claim
252 words
A circuit arrangement comprised of: a send path carrying a send signal; a receiving path carrying a received signal; an adaptive filter; a compensator in the received path; a digital/analog converter; a transmission unit; and a transmission line attached to the transmission unit, wherein over the transmission line at least the send signal, the received signal and echo signal portions are transmitted, with the send path and the received path being connected with the transmission unit; with the send signal, for the estimation of the echo signal, being transmitted to the adaptive filter, wherein the estimated digital echo signal is transmitted to the compensator for the reduction of the echo signal portion in the received path, with the send signal being impressed upon the digital/analog converter and a send filter being interposed in the send path, between the digital/analog converter and the transmission unit, wherein the adaptive filter is comprised of at least an FIR (Finite Impulse Response) filter portion, with the FIR filter portion being of the storage compensation type, wherein in the FIR filter portion (FIR) at least one storage element and at least one digit delay element are provided, and when several digit delay elements are provided the several digit delay elements are switched in series with the first digit delay element being impressed with the send signal, wherein the adaptive filter is additionally comprised of an IIR (Infinite Impulse Response) filter portion, and wherein the send filter has a transfer function T(s)=T 1 (s)*T 2 (s), wherein: ##EQU9##
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-14 | 2001-01-13 | 2001-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-14 | 2005-01-13 | 2005-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-14 | 2009-01-13 | 2009-07-15 | $7700.00 | Window Closed / Lapsed |