US5646686A
Expired / Lapsed
US
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Methods and apparatus for reducing drift in video decoders
Assignee: Hitachi America Ltd
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Filing: 1996-09-27
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Granted: 1997-07-08
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Expires: 2016-09-27
Abstract
Abstract A video decoder capable of downsampling full resolution images on a block by block basis regardless of the downsampling rate is disclosed. When the applied downsampling rate does not divide evenly into the number of pixel values included in a block in the dimension being downsampled, the decoder generates a partial pixel value. A partial pixel value represents a portion of the information used to represent a pixel of an image. In contrast, a full or complete pixel value is a value represents all the information used to represent a pixel of an image. The generated partial pixel value is stored and then added to another partial pixel value generated by downsampling another block of pixel values corresponding to a portion of a full resolution image. Numerous drift reduction processing techniques applicable to downsampling decoders are disclosed. Many of these processing techniques are applicable to decoders which perform full order IDCTs as well as reduced order IDCTs. In one embodiment, spatial filtering is applied to anchor frames as part of the motion compensation process in order to reduce or eliminate drift. The spatial filtering is performed as a function of the location of the current block being decoded, the location within the anchor frame of the data being used for prediction purposes, and the motion vector being applied. Various drift reduction techniques applicable to interlaced and non-interlaced images are also described with drift reduction processing for interlaced images being applied differently than for non-interlaced images. In order to maximize the benefit from limited drift reduction processing resources, in various embodiments the amount of drift reduction processing is varied depending on the type of data being processed, e.g., more drift reduction processing is performed on uni-directionally encoded blocks than bi-directionally encoded blocks.
Inventors
- 👤 Larry A. Pearlstein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:41
CPC Classifications
H; H04; H04N; H04N19/00; G; G06; G06T; G06T3/00; G06T3/40; G06T3/4007; G06T3/4084; G11; G11B; G11B5/00; G11B5/008; G11B5/00813; G11B5/00847; G11B5/0086; H03; H03M; H03M7/00; H04N19/10; H04N19/102; H04N19/117; H04N19/124; H04N19/132; H04N19/134; H04N19/136; H04N19/137; H04N19/139; H04N19/157; H04N19/159; H04N19/16; H04N19/162; H04N19/169; H04N19/17; H04N19/172; H04N19/176; H04N19/18; H04N19/184; H04N19/189; H04N19/192; H04N19/40; H04N19/42; H04N19/423; H04N19/426; H04N19/427; H04N19/428; H04N19/44; H04N19/46; H04N19/48; H04N19/50; H04N19/503; H04N19/51; H04N19/513; H04N19/587; H04N19/59; H04N19/60; H04N19/61; H04N19/70; H04N19/80; H04N19/82; H04N19/90; H04N21/00; H04N21/20; H04N21/23; H04N21/231; H04N21/23106; H04N21/234; H04N21/2343; H04N21/236; H04N21/25; H04N21/266; H04N21/2662; H04N21/40; H04N21/41; H04N21/426; H04N21/43; H04N21/431; H04N21/4312; H04N21/4316; H04N21/432; H04N21/4325; H04N21/434; H04N21/438; H04N21/4382; H04N21/44; H04N21/4402; H04N21/440254; H04N21/440263; H04N21/45; H04N21/462; H04N21/4621; H04N5/00; H04N5/44; H04N5/445; H04N5/45; H04N5/46; H04N9/00; H04N9/79; H04N9/80; H04N9/804; H04N9/8042; G11B15/00; G11B15/02; G11B15/12; G11B15/125; G11B15/18; G11B15/1808; G11B15/1875; G11B15/46; G11B15/467; G11B15/4673; H04N19/13; H04N19/30; H04N19/91; H04N5/76; H04N5/78; H04N5/782; H04N5/7824; H04N5/7826; H04N5/78263; H04N9/82; H04N9/8205; H04N9/8227
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
84 words
A method of downsampling multiple groups of complete pixel values in at least a first dimension by a factor of N, where N is a positive number, comprising the steps of: downsampling a first group of complete pixel values by N to generate a first partial pixel value; downsampling at least a second group of full pixel values by N to generate a second partial pixel value; and combining at least the first and second partial pixel values to form a complete pixel value.
Claim 2
Independent Claim
84 words
A method of downsampling multiple groups of complete pixel values in at least a first dimension by a factor of N, where N is a positive number, comprising the steps of: downsampling a first group of complete pixel values by N to generate a first partial pixel value; downsampling at least a second group of full pixel values by N to generate a second partial pixel value; and combining at least the first and second partial pixel values to form a complete pixel value.
Claim 3
Dependent Claim
30 words
The method of claim 1, wherein the first and second groups of complete pixel values are rows of pixel values which are located in different blocks of complete pixel values.
Claim 4
Dependent Claim
26 words
The method of claim 2, further comprising the step of: storing the first partial pixel value prior to combining it with the second partial pixel value.
Claim 5
Dependent Claim
146 words
The method of claim 3, wherein each block of complete pixel values includes multiple rows of pixel values, wherein the first and second groups of complete pixel values are the first and second rows of pixel values located in first and second blocks, respectively, the method further comprising the steps of: downsampling a third group of complete pixel values by N to generate a third partial pixel value, the third group of pixel values being a second row of complete pixel values included in the first block; storing the third partial pixel value; downsampling a fourth group of complete pixel values by N to generate a fourth partial pixel value, the fourth group of complete pixel values being a second row of complete pixel values included in the first block; and combining the third and fourth partial pixel values to generate a second complete pixel value.
Claim 6
Dependent Claim
42 words
The method of claim 4, further comprising the steps of: incorporating the first and second complete pixel values into a third block of complete pixel values which is a downsampled representation of at least the first and second blocks complete pixel values.
Claim 7
Dependent Claim
35 words
The method of claim 4, further comprising the step of: downsampling the first and second blocks of complete pixel values in a second dimension by a factor of X, where X is a positive number.
Claim 8
Dependent Claim
56 words
The method of claim 6, wherein the step of downsampling the first and second blocks of pixel values in the second dimension includes the step of: generating partial pixel values by downsampling the first and second blocks of complete pixel values in the second dimension; and combining the partial pixel values to form complete pixel values.
Claim 9
Dependent Claim
48 words
The method of claim 7, wherein the first dimension is the horizontal direction and the second dimension is the vertical direction; wherein the first and second blocks of complete pixel values are 8×8 blocks of video data and wherein each pixel value includes data representing a single pixel.
Claim 10
Dependent Claim
90 words
A video decoder circuit, comprising: a full order inverse discrete cosine transform circuit; a downsampler coupled to the full order inverse discrete cosine transform circuit; a frame memory for storing anchor frame data coupled to the downsampler; and a first motion compensated prediction filter module including a first spatially variant filter circuit coupled to the anchor frame memory for filtering anchor frame data representing at least a portion of an anchor frame to thereby reduce the amount of drift that will result in an a video frame being generated therefrom.
Claim 11
Dependent Claim
90 words
A video decoder circuit, comprising: a full order inverse discrete cosine transform circuit; a downsampler coupled to the full order inverse discrete cosine transform circuit; a frame memory for storing anchor frame data coupled to the downsampler; and a first motion compensated prediction filter module including a first spatially variant filter circuit coupled to the anchor frame memory for filtering anchor frame data representing at least a portion of an anchor frame to thereby reduce the amount of drift that will result in an a video frame being generated therefrom.
Claim 12
Dependent Claim
56 words
The video decoder circuit of claim 9, further comprising: a syntax parser and variable length decoder circuit coupled to the filter control circuit and for supplying thereto macroblock type information relevant to the frame being generated; and wherein the filter control circuit also controls the spatially variant filter as a function of the macroblock type information.
Claim 13
Dependent Claim
49 words
The video decoder circuit of claim 9, further comprising: a filter control circuit for controlling the spatially variant filter circuit to perform reduced computational filtering when the video frame is being generated using interpolated prediction than is performed when the video frame is being generated using one way prediction.
Claim 14
Dependent Claim
102 words
The video decoder circuit of claim 9, wherein the portion of the anchor frame being filtered was generated from data that was previously coded using a field type discrete cosine transform operation or a frame type discrete cosine transform operation, the decoder circuit further comprising: an auxiliary memory coupled to the frame memory for storing information on the type of discrete cosine transform operation previously used to code the data stored in the frame memory; and a filter control circuit for controlling the spatially variant filter circuit as a function of the discrete cosine transform type information stored in the auxiliary memory.
Claim 15
Dependent Claim
74 words
The video decoder circuit of claim 9, wherein the portion of the anchor frame being filtered was generated from data that was previously coded using a field type discrete cosine transform operation or a frame type discrete cosine transform operation, the decoder circuit further comprising: a filter control circuit for controlling the spatially variant filter circuit as a function of the discrete cosine transform type previously used to code the anchor frame being filtered.
Claim 16
Dependent Claim
27 words
The video decoder circuit of claim 9, further comprising: a filter control circuit for controlling the spatially variant filter circuit as a function of a motion vector.
Claim 17
Dependent Claim
52 words
The video decoder circuit of claim 14, wherein the video frame being generated is one of a plurality of frame types; and wherein the filter control circuit varies the amount of filtering performed by the spatially variant filter to reduce drift as a function of the type of video frame being generated.
Claim 18
Dependent Claim
71 words
The video decoder circuit of claim 14, wherein the video frame being generated uses either one way prediction or interpolated prediction; and wherein the filter control circuit varies the amount of filtering performed by the spatially variant filter so that less computationally complex filtering is performed by the spatially variant filter when the video frame being generated uses interpolated prediction than when the video frame being generated uses one way prediction.
Claim 19
Dependent Claim
99 words
The video decoder circuit of claim 14, wherein the video frame being generated uses either one way prediction or interpolated prediction; and wherein the motion compensated prediction filter module includes: i. a first prediction filter module including the first spatially variant filter circuit the first spatially variant filter circuit; and ii. a second prediction filter module including a second spatially variant filter circuit which is less computationally complex than the first spatially variant filter circuit, the second spatially variant filter circuit being used to filter anchor frame picture data used to produce video frames being generated using interpolated prediction.
Claim 20
Dependent Claim
19 words
The video decoder of claim 14, further comprising: a DCT truncation circuit coupled to the full order IDCT circuit.
Claim 21
Dependent Claim
42 words
The video decoder circuit of claim 18, further comprising: means for storing partial pixel values coupled to the downsampler; and means for combining a stored partial pixel value with a subsequently generated partial pixel value to generate a full pixel value therefrom.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-07 | 2001-01-06 | 2001-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-07 | 2005-01-06 | 2005-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-07 | 2009-01-06 | 2009-07-08 | $7700.00 | Window Closed / Lapsed |