US5644528A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile memory having a cell applying to multi-bit data by multi-layered floating gate architecture and programming method for the same
Assignee: NXP USA Inc
•
Filing: 1995-11-21
•
Granted: 1997-07-01
•
Expires: 2015-11-21
Abstract
Abstract An object of the present invention is to contribute to increase of storage capacity of a memory. A nonvolatile memory having a cell applying to multi-bit data by multi-layered floating gate architecture. The memory has a storage cell transistor which comprises a semiconductor substrate 1, source 2, drain 3 and control gate 5. The storage cell transistor, furthermore comprises a plurality of floating gates 4B 1 -4B n which are arranged in order between a channel and the control gate. Two or more bits data can be saved per one storage cell. According to this architecture, an integration factor per one storage cell leaps upward since a necessary number of floating gates are stacked to overlie each other, the particular number corresponding to the number of bits to be stored therein.
Inventors
- 👤 Toshiaki Kojima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:10
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C16/0475; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C16/0408; G11C16/0441; G11C16/0458; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5612
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
65 words
A non-volatile memory having a cell applying to multi-bit data by multi-layered floating gate architecture, which is characterized by a storage cell transistor comprising: source and drain being formed in a semiconductor substrate distantly from each other so as to form a channel therebetween; a control gate facing said channel; a plurality of floating gates arranged in order between said channel and said control gate.
Claim 2
Dependent Claim
65 words
A non-volatile memory having a cell applying to multi-bit data by multi-layered floating gate architecture, which is characterized by a storage cell transistor comprising: source and drain being formed in a semiconductor substrate distantly from each other so as to form a channel therebetween; a control gate facing said channel; a plurality of floating gates arranged in order between said channel and said control gate.
Claim 3
Dependent Claim
300 words
A non-volatile memory having a cell applying to multi-bit data by multi-layered floating gate architecture, which is characterized by a storage cell transistor comprising: source and drain being formed in a semiconductor substrate distantly from each other so as to form a channel therebetween; and a control gate facing said channel, said storage cell transistor further comprising: at least one first floating gate having a width extending from said source to said drain, said at least one first floating gate extending in a direction crossing to the separating direction of said source and drain, and arranged in order between said channel and said control gate; a first program gate facing one of the extending ends of said first floating gate from said channel; a first erasure gate facing the other extending end of said first floating gate from said control gate; at least one second floating gate facing said first floating gate, said at least one second floating gate extending in a direction crossing to the extending direction of said first floating gate, arranged in order between said channel and said control gate and overlapping a portion of the first floating gate, said first and second floating gates arranged in alternating order in their respective extending directions between said channel and said control gate; a second program gate facing one of the extending ends of said second floating gate from said channel; a second erasure gate facing the other extending end of said second floating gate from said control gate; a first bias gate facing said first floating gate from said control gate in locations excluding said overlapping locations where said first and second floating gates overlap with each other; and a second bias gate facing said second floating gate from said control gate in locations excluding said overlapping locations.
Claim 4
Dependent Claim
300 words
A non-volatile memory having a cell applying to multi-bit data by multi-layered floating gate architecture, which is characterized by a storage cell transistor comprising: source and drain being formed in a semiconductor substrate distantly from each other so as to form a channel therebetween; and a control gate facing said channel, said storage cell transistor further comprising: at least one first floating gate having a width extending from said source to said drain, said at least one first floating gate extending in a direction crossing to the separating direction of said source and drain, and arranged in order between said channel and said control gate; a first program gate facing one of the extending ends of said first floating gate from said channel; a first erasure gate facing the other extending end of said first floating gate from said control gate; at least one second floating gate facing said first floating gate, said at least one second floating gate extending in a direction crossing to the extending direction of said first floating gate, arranged in order between said channel and said control gate and overlapping a portion of the first floating gate, said first and second floating gates arranged in alternating order in their respective extending directions between said channel and said control gate; a second program gate facing one of the extending ends of said second floating gate from said channel; a second erasure gate facing the other extending end of said second floating gate from said control gate; a first bias gate facing said first floating gate from said control gate in locations excluding said overlapping locations where said first and second floating gates overlap with each other; and a second bias gate facing said second floating gate from said control gate in locations excluding said overlapping locations.
Claim 5
Dependent Claim
61 words
A non-volatile memory according to claim 2, wherein the surface of said fist program gate facing said first floating gate, the surface of said second program gate facing said second floating gate, the surface of said first floating gate facing said first erasure gate, and the surface of said second floating gate facing said second erasure gate have asperities formed thereon.
Claim 6
Dependent Claim
23 words
A non-volatile memory according to claim 2, wherein the extending directions of said first and second floating gates are perpendicular to each other.
Claim 7
Dependent Claim
68 words
A method of programming the non-volatile memory according to claim 2, 3 or 4, said method comprising the steps of: applying a positive high voltage to said first and second bias gates; and setting said first and second program gates and said first and second erasure gates to a predetermined reference potential, and; injecting electrons produced by the resulting tunnel current into said first and second floating gates.
Claim 8
Dependent Claim
55 words
A method of erasing information stored in the non-volatile memory according to claim 2, 3, or 4, said method comprising the steps of: applying a positive high voltage to said first and second erasure gates; and setting said first and second bias gates and said first and second program gates to a predetermined reference potential.
References Cited (Backward Citations)
US5159570A
Cited
US5422845A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-30 | 2000-12-30 | 2001-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-30 | 2004-12-30 | 2005-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-30 | 2008-12-30 | 2009-07-01 | $7700.00 | Window Closed / Lapsed |