Integrated audio decoder system and method of operation

Claim 2

A data processing system, comprising: a microprocessor host circuit; an integrated audio decoder system coupled to said microprocessor host circuit and operable to receive encoded data and extract selected encoded audio data from said encoded data, said integrated audio decoder system further operable to decode said selected encoded audio data and to output said decoded audio data; further comprising: a system reference clock register for maintaining a copy of a reference time; a plurality of functional processing blocks, each of said functional processing blocks operable to manipulate a block of said encoded audio data asynchronously to said system reference clock; a plurality of buffers, each of said buffers operable to store a plurality of said blocks of encoded audio data, said plurality of buffers being interspersed among said plurality of functional processing blocks to form an interconnected chain such that each of said buffers is connected between a different pair of said functional processing blocks and operable to allow each functional block of said pair of functional blocks to store and retrieve said blocks of encoded audio data to and from said buffer connected directly to said functional block such that all of said buffers can be accessed simultaneously by said respective functional blocks; wherein each of said blocks of encoded audio data and decoded audio data is related to a presentation time stamp; and a digital to analog converter coupled to said integrated audio decoder system and operable to receive said decoded audio data synchronously with said system reference clock according to said presentation time stamp and convert said decoded audio data into analog signals.

Claim 3

The data processing system of claim 1 wherein said integrated audio decoder system further comprises: a host interface circuit operable to couple said integrated audio decoder system to said microprocessor host circuit; one of said functional processing blocks is a system decoder circuit coupled to said host interface and operable to receive said encoded data, extract said encoded audio data from said encoded data, and output said encoded audio data; one of said buffers is an input buffer circuit coupled to said system decoder and operable to receive, store, and output said encoded audio data; one of said functional processing blocks is an audio decoder circuit coupled to said input buffer circuit and operable to retrieve said encoded audio data from said input buffer circuit, decode said encoded audio data, and to output decoded audio data; one of said buffers is an arithmetic unit buffer circuit coupled to said audio decoder and operable to receive, store, and output said decoded audio data; one of said functional processing blocks is an arithmetic unit circuit coupled to said arithmetic unit buffer and operable to retrieve said decoded audio data from said arithmetic unit buffer circuit; dequantize, transform, and filter said decoded audio data, and to output filtered audio data; one of said buffers is an output buffer circuit coupled to said arithmetic unit circuit and operable to receive, store, and output said filtered audio data; and one of said functional processing blocks is an output circuit coupled to said output buffer circuit and said digital to analog converter and operable to retrieve said filtered data from said output buffer circuit and to output said filtered data to said digital to analog converter.

Claim 4

The data processing system of claim 2 wherein said host interface circuit, said system decoder circuit, said input buffer circuit, said audio decoder circuit, said arithmetic buffer circuit, said arithmetic unit circuit, said output buffer circuit, and said output circuit are all disposed on a single semiconductor substrate.

Claim 5

The data processing system of claim 2 wherein said audio decoder block comprises a microprogrammed circuit and a microprogram memory operable to store microcode routines defining the operations performed by said audio decoder circuit.

Claim 6

The data processing system of claim 2 wherein said arithmetic unit comprises a state machine driven circuit operable to sequentially dequantize, transform and filter said decoded audio data to form said filtered audio data.

Claim 7

The data processing system of claim 2 and further comprising: an external buffer circuit coupled to said system decoder circuit and said audio decoder circuit and operable to receive, store and output additional encoded audio data; said system decoder circuit and said audio decoder circuit operable to sense the presence of said external buffer circuit and to utilize said external buffer circuit to store additional encoded audio data if said external buffer circuit is present.

Claim 8

The data processing system of claim 6 wherein said system decoder circuit, said input buffer circuit, and said audio decoder circuit are disposed on a first semiconductor substrate and said external buffer circuit is disposed on a second semiconductor substrate.

Claim 9

The data processing system of claim 2 wherein said arithmetic unit circuit is operable to form and output pulse code modulated data for storage in said output buffer circuit, said digital to analog converter circuit operable to receive said pulse code modulated data and to convert said pulse code modulated data to analog signals.

Claim 10

The data processing system of claim 2 wherein said integrated audio decoder system further comprises a plurality of control and status registers accessible by said microprocessor host circuit and said audio decoder circuit.

Claim 11

The data processing system of claim 1 wherein said microprocessor host circuit is operable to receive a serial encoded bit stream and output the information contained in said serial encoded bit stream to said audio decoder system through a plurality of parallel signal lines, said audio decoder system operable to receive said encoded data through said parallel signal lines.

Claim 12

The data processing system of claim 1 wherein said audio decoder system is operable to receive said encoded data through a serial encoded bit stream input into said audio decoder system.

Claim 13

An audio decoding system, comprising: a host interface circuit operable to receive external signals including blocks of encoded data; a system reference clock register for maintaining a copy of a reference time, wherein each of said blocks of encoded data is related to a presentation time stamp; a plurality of functional processing blocks, each of said functional processing blocks operable to manipulate a block of said encoded data asynchronously to said system reference clock; wherein one of said functional blocks is a system decoder circuit coupled to said host interface and operable to receive said encoded data, extract encoded audio data from said encoded data stream, and output said encoded audio data; an input buffer circuit coupled to said system decoder and operable to receive, store, and output said encoded audio data; wherein one of said functional blocks is an audio decoder circuit coupled to said input buffer circuit and operable to retrieve said encoded audio data from said input buffer circuit, decode said encoded audio data, and to output decoded audio data; an arithmetic unit buffer circuit coupled to said audio decoder and operable to receive, store, and output said decoded audio data; wherein one of said functional blocks is an arithmetic unit circuit coupled to said arithmetic unit buffer and operable to retrieve said decoded audio data from said arithmetic unit buffer circuit; dequantize, transform, and filter said decoded audio data, and to output filtered audio data; an output buffer circuit coupled to said arithmetic unit circuit and operable to receive, store, and output said filtered audio data; and wherein one of said functional blocks is an output circuit coupled to said output buffer circuit and operable to retrieve said filtered data from said output buffer circuit synchronously with said system reference clock according to said presentation time stamp and to output said filtered data.

Claim 14

An audio decoding system, comprising: a host interface circuit operable to receive external signals including blocks of encoded data; a system reference clock register for maintaining a copy of a reference time, wherein each of said blocks of encoded data is related to a presentation time stamp; a plurality of functional processing blocks, each of said functional processing blocks operable to manipulate a block of said encoded data asynchronously to said system reference clock; wherein one of said functional blocks is a system decoder circuit coupled to said host interface and operable to receive said encoded data, extract encoded audio data from said encoded data stream, and output said encoded audio data; an input buffer circuit coupled to said system decoder and operable to receive, store, and output said encoded audio data; wherein one of said functional blocks is an audio decoder circuit coupled to said input buffer circuit and operable to retrieve said encoded audio data from said input buffer circuit, decode said encoded audio data, and to output decoded audio data; an arithmetic unit buffer circuit coupled to said audio decoder and operable to receive, store, and output said decoded audio data; wherein one of said functional blocks is an arithmetic unit circuit coupled to said arithmetic unit buffer and operable to retrieve said decoded audio data from said arithmetic unit buffer circuit; dequantize, transform, and filter said decoded audio data, and to output filtered audio data; an output buffer circuit coupled to said arithmetic unit circuit and operable to receive, store, and output said filtered audio data; and wherein one of said functional blocks is an output circuit coupled to said output buffer circuit and operable to retrieve said filtered data from said output buffer circuit synchronously with said system reference clock according to said presentation time stamp and to output said filtered data.

Claim 15

The audio decoding system of claim 12 wherein said host interface circuit, said system decoder circuit, said input buffer circuit, said audio decoder circuit, said arithmetic buffer circuit, said arithmetic unit circuit, said output buffer circuit, and said output circuit are all disposed on a single semiconductor substrate.

Claim 16

The audio decoding system of claim 12 wherein said audio decoder circuit comprises a microprogrammed circuit and a microprogram memory operable to store microcode routines defining the operations performed by said audio decoder circuit.

Claim 17

The audio decoding system of claim 12 wherein said arithmetic unit comprises a state machine driven circuit operable to sequentially dequantize, transform and filter said decoded audio data to form said filtered audio data.

Claim 18

The audio decoding system of claim 12 and further comprising: an external buffer circuit coupled to said system decoder circuit and said audio decoder circuit and operable to receive, store and output additional encoded audio data; said system decoder circuit and said audio decoder circuit operable to sense the presence of said external buffer circuit and to utilize said external buffer circuit to store additional encoded audio data if said external buffer circuit is present.

Claim 19

The audio decoding system of claim 16 wherein said system decoder circuit, said input buffer circuit, and said audio decoder circuit are disposed on a first semiconductor substrate and said external buffer circuit is disposed on a second semiconductor substrate.

Claim 20

The audio decoding system of claim 12 wherein said arithmetic unit circuit is operable to form and output pulse code modulated data for storage in said output buffer circuit, the audio decoding system further comprising a digital to analog converter circuit coupled to said output circuit and operable to receive said pulse code modulated data and to convert said pulse code modulated data to analog signals.

Claim 21

The audio decoding system of claim 12 and further comprising a plurality of control and status registers accessible by a microprocessor host circuit and said audio decoder circuit.

Claim 22

The audio decoding system of claim 12 wherein said audio decoding system is operable to receive said encoded data through a serial encoded bit stream input into said host interface circuit.