Algorithmic analog-to-digital converter having redundancy and digital calibration

Claim 3

The method as claimed in claim 1, wherein said method further includes measuring the loop gain of said algorithmic converter to determine a measured value of the loop gain, and setting said radix to the measured value of the loop gain.

Claim 4

The method as claimed in claim 1, wherein said method further includes setting said analog input signal to a first reference voltage, operating said algorithmic converter to determine a first set of digits of said redundant digital code corresponding to said first reference voltage, setting said analog input signal to a second reference voltage, operating said algorithmic converter to determine a second set of digits of said redundant digital code corresponding to said second reference voltage, and from said first set of digits and said second set of digits, computing said radix so that said radix is substantially equal to said loop gain.

Claim 5

The method as claimed in claim 1, wherein said loop gain is approximately 1.8.

Claim 6

The method as claimed in claim 1, wherein said loop gain is approximately 1.75.

Claim 9

The method as claimed in claim 6, wherein said polynomial is computed with a constant term, and said method includes setting said analog input signal to a zero voltage level, operating said redundant algorithmic converter and said digital computation unit to convert said zero voltage level to an offset value, and setting said constant term to said offset value.

Claim 10

The method as claimed in claim 6, wherein said algorithmic converter has a maximum loop offset of V offmax and a reference voltage of V ref , and said method includes selecting said loop gain to be less than 2/(1+V offmax /V ref ).

Claim 11

The method as claimed in claim 6, wherein said algorithmic converter has switched capacitors, and said method includes selecting a ratio of capacitance values of said switched capacitors in order to establish said loop gain.

Claim 12

The method as claimed in claim 6, wherein said redundant digital code is a binary code, and each of said coefficients of said polynomial specified by said redundant digital code has either a first value when the corresponding bit of said binary code has a first binary state or a second value when a corresponding bit of said binary code has a second binary state.

Claim 17

The method as claimed in claim 12 wherein said method includes solving said polynomial equation by successive approximations.

Claim 20

The method as claimed in claim 14, wherein said method further includes averaging a number of polynomials computed from digital codes from a plurality of conversions of said reference voltage by said algorithmic converter to compute said digital output signal for comparison to said reference value.

Claim 21

The method as claimed in claim 15, wherein said method further includes computing said polynomial by operating an adder/subtractor to accumulate powers of said radix in an accumulator register, said code specifies an accumulation operation performed for each power of said radix, and the averaging of a number of polynomials is performed by inhibiting resetting of said accumulator register between computations of said polynomial.

Claim 26

The method as claimed in claim 18, which includes alternately performing each of steps c) and d) a plurality of times so that when said analog input signal is set to said first reference voltage, said digital output signal becomes substantially equal to said first reference value, and when said analog input signal is set to said second reference voltage, said digital output signal becomes substantially equal to said second reference value.

Claim 27

A successive-approximation method of adjusting gain and offset of a converter so that a first input reference value becomes converted to a first output reference value, and a second input reference value becomes converted to a second output reference value, wherein the gain and offset adjustments are not independent, said converter is responsive to a gain value for adjusting the gain of the converter, and said converter is responsive to an offset value for adjusting the offset of the converter, said method comprising the steps of: (a) setting said gain value to an initial value; (b) setting said offset value to an initial value corresponding to said first output reference value, and operating said converter to convert said first input reference value to a converted value to determine a new value for said offset value, and setting said offset value to said new value for said offset value; and (c) operating said converter to convert said second input reference value to a converted value, comparing said converted value to said second output reference value, and adjusting a bit of said gain value based on the comparing of said converted output value to said second output reference value; wherein said steps (b) and (c) are repeated so that step (c) successively adjusts a series of consecutive bits of said gain value beginning with adjustment of a more significant bit and ending with adjustment of a less significant bit.

Claim 28

A successive-approximation method of adjusting gain and offset of a converter so that a first input reference value becomes converted to a first output reference value, and a second input reference value becomes converted to a second output reference value, wherein the gain and offset adjustments are not independent, said converter is responsive to a gain value for adjusting the gain of the converter, and said converter is responsive to an offset value for adjusting the offset of the converter, said method comprising the steps of: (a) setting said gain value to an initial value; (b) setting said offset value to an initial value corresponding to said first output reference value, and operating said converter to convert said first input reference value to a converted value to determine a new value for said offset value, and setting said offset value to said new value for said offset value; and (c) operating said converter to convert said second input reference value to a converted value, comparing said converted value to said second output reference value, and adjusting a bit of said gain value based on the comparing of said converted output value to said second output reference value; wherein said steps (b) and (c) are repeated so that step (c) successively adjusts a series of consecutive bits of said gain value beginning with adjustment of a more significant bit and ending with adjustment of a less significant bit.

Claim 29

The method as claimed in claim 20, wherein said converter is an algorithmic analog-to-digital converter system including an algorithmic converter for converting an analog input signal to a series of digits and a digital computation unit for computing a polynomial of a radix value, said digits being coefficients of said polynomial, and said method includes adjusting said radix value in response to adjustment of said gain value.

Claim 30

The method as claimed in claim 21, wherein said polynomial includes a constant coefficient, and said method includes adjusting said constant coefficient in response to adjustment of said offset value.

Claim 31

An algorithmic converter system comprising: an algorithmic converter having a loop gain substantially less than two for converting an analog input signal to a redundant digital code; and a digital computation unit for converting said redundant digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, wherein said redundant digital code specifies coefficients of said polynomial; wherein said redundant digital code is a binary code, and each of said coefficients of said polynomial specified by said redundant digital code has either a first value when the corresponding bit of said binary code has a first binary state or a second value when a corresponding bit of said binary code has a second binary state; and wherein said first value is +1 and said second value is -1.

Claim 32

An algorithmic converter system comprising: an algorithmic converter having a loop gain substantially less than two for converting an analog input signal to a redundant digital code; and a digital computation unit for converting said redundant digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, wherein said redundant digital code specifies coefficients of said polynomial; wherein said redundant digital code is a binary code, and each of said coefficients of said polynomial specified by said redundant digital code has either a first value when the corresponding bit of said binary code has a first binary state or a second value when a corresponding bit of said binary code has a second binary state; and wherein said first value is +1 and said second value is -1.

Claim 33

An algorithmic converter system comprising: an algorithmic converter having a loop gain substantially less than two for converting an analog input signal to a redundant digital code; and a digital computation unit for converting said redundant digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, wherein said redundant digital code specifies coefficients of said polynomial; and wherein said redundant algorithmic converter is a redundant signed digit (RSD) algorithmic converter so that said redundant digital code is a three-state code, and each of said coefficients of said polynomial specified by said three-state code has either a first value when a corresponding digit of said three-state code has a first state or a second value when the corresponding digit of said three-state code has a second state or a third value when the corresponding digit of said three-state code has a third state.

Claim 34

An algorithmic converter system comprising: an algorithmic converter having a loop gain substantially less than two for converting an analog input signal to a redundant digital code; and a digital computation unit for converting said redundant digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, wherein said redundant digital code specifies coefficients of said polynomial; and wherein said redundant algorithmic converter is a redundant signed digit (RSD) algorithmic converter so that said redundant digital code is a three-state code, and each of said coefficients of said polynomial specified by said three-state code has either a first value when a corresponding digit of said three-state code has a first state or a second value when the corresponding digit of said three-state code has a second state or a third value when the corresponding digit of said three-state code has a third state.

Claim 35

The algorithmic converter as claimed in claim 24, wherein said first value is +1, said second value is 0, and said third value is -1.

Claim 36

An algorithmic converter system comprising: an algorithmic converter having a loop gain substantially less than two for converting an analog input signal to a redundant digital code; and a digital computation unit for converting said redundant digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, wherein said redundant digital code specifies coefficients of said polynomial; and wherein said digital computation unit includes a power table memory containing powers of said radix, an accumulator register, and an adder/subtractor unit; and said adder/subtractor unit has an output coupled to said accumulator register for loading a result of said adder/subtractor unit in said accumulator register, a first input coupled to said accumulator register for receiving a previous result having been loaded into said accumulator register, a second input coupled to said power table memory for receiving a power of said radix from said power table memory, and a control input responsive to said redundant digital code for operating said adder/subtractor as either an adder or a subtractor for computing said polynomial.

Claim 37

An algorithmic converter system comprising: an algorithmic converter having a loop gain substantially less than two for converting an analog input signal to a redundant digital code; and a digital computation unit for converting said redundant digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, wherein said redundant digital code specifies coefficients of said polynomial; and wherein said digital computation unit includes a power table memory containing powers of said radix, an accumulator register, and an adder/subtractor unit; and said adder/subtractor unit has an output coupled to said accumulator register for loading a result of said adder/subtractor unit in said accumulator register, a first input coupled to said accumulator register for receiving a previous result having been loaded into said accumulator register, a second input coupled to said power table memory for receiving a power of said radix from said power table memory, and a control input responsive to said redundant digital code for operating said adder/subtractor as either an adder or a subtractor for computing said polynomial.

Claim 38

The algorithmic converter system as claimed in claim 26, wherein said digital computation unit includes a register for storing a value that specifies said radix, and means for determining said value that specifies said radix so that said digital output signal has a reference value when said analog input is at a reference voltage level.

Claim 39

The algorithmic converter system as claimed in claim 27, wherein said reference value is a full-scale value of said digital output signal.

Claim 40

The algorithmic converter system as claimed in claim 27, wherein said digital computation unit further includes a register for storing an offset value specifying a constant coefficient for said polynomial, and means for computing said offset value so that said digital output signal has a value of substantially zero when said analog input signal is at a zero voltage level.

Claim 41

An algorithmic converter system comprising: an algorithmic converter having a loop gain for converting an analog input signal to a digital code; and a digital computation unit for converting said digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said digital code specifying coefficients of said polynomial; wherein said digital computation unit includes a radix register for storing a value that specifies said radix, and means for determining said value that specifies said radix so that said digital output has a reference value when said analog input is at a reference voltage level; and wherein said means for determining said value that specifies said radix includes means for setting said analog input signal to said reference voltage and means for adjusting said value in said radix register so that said digital output signal assumes a value that is substantially equal to said reference value.

Claim 42

An algorithmic converter system comprising: an algorithmic converter having a loop gain for converting an analog input signal to a digital code; and a digital computation unit for converting said digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said digital code specifying coefficients of said polynomial; wherein said digital computation unit includes a radix register for storing a value that specifies said radix, and means for determining said value that specifies said radix so that said digital output has a reference value when said analog input is at a reference voltage level; and wherein said means for determining said value that specifies said radix includes means for setting said analog input signal to said reference voltage and means for adjusting said value in said radix register so that said digital output signal assumes a value that is substantially equal to said reference value.

Claim 43

The algorithmic converter system as claimed in claim 30, wherein said reference value is a full-scale value of said digital output signal.

Claim 44

The algorithmic converter system as claimed in claim 30, wherein said means for adjusting includes means for successively adjusting individual bits in said radix register beginning with a most significant bit in said radix register and successively re-computing said digital output signal and comparing the re-computed digital output signal to said reference value and selectively re-adjusting each adjusted bit in response to the comparing of the re-computed digital output signal to said reference value.

Claim 45

The algorithmic converter system as claimed in claim 30, wherein said digital computation unit further includes an offset register for storing an offset value specifying a constant coefficient for said polynomial, and means for computing said offset value so that said digital output has a value of substantially zero when said analog input is at a zero voltage level.

Claim 46

An algorithmic converter system comprising: an algorithmic converter having a loop gain for converting an analog input signal to a digital code; and a digital computation unit for converting said digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said digital code specifying coefficients of said polynomial; wherein said digital computation unit includes a radix register for storing a value that specifies said radix, and means for determining said value that specifies said radix so that said digital output has a reference value when said analog input is at a reference voltage level; and wherein said means for determining said value in said radix register includes means for computing an average digital output value from a plurality of digital codes from a plurality of conversions of said analog input signal by said algorithmic converter when said analog input signal is set to said reference voltage, and means for adjusting said value in said radix register so that said average digital output value becomes substantially equal to said reference value.

Claim 47

An algorithmic converter system comprising: an algorithmic converter having a loop gain for converting an analog input signal to a digital code; and a digital computation unit for converting said digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said digital code specifying coefficients of said polynomial; wherein said digital computation unit includes a radix register for storing a value that specifies said radix, and means for determining said value that specifies said radix so that said digital output has a reference value when said analog input is at a reference voltage level; and wherein said means for determining said value in said radix register includes means for computing an average digital output value from a plurality of digital codes from a plurality of conversions of said analog input signal by said algorithmic converter when said analog input signal is set to said reference voltage, and means for adjusting said value in said radix register so that said average digital output value becomes substantially equal to said reference value.

Claim 48

An algorithmic converter system comprising: an algorithmic converter having a loop gain for converting an analog input signal to a digital code; and a digital computation unit for converting said digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said digital code specifying coefficients of said polynomial; wherein said digital computation unit includes a radix register for storing a value that specifies said radix, and means for determining said value that specifies said radix so that said digital output has a reference value when said analog input is at a reference voltage level; wherein said digital computation unit further includes an offset register for storing an offset value specifying a constant coefficient for said polynomial, and means for computing said offset value so that said digital output has a value of substantially zero when said analog input is at a zero voltage level; and wherein said means for determining said offset value includes means for setting said analog input signal to said zero voltage level and operating said algorithmic converter and said digital computation unit to convert said zero voltage level to said offset value, and said means for determining said value that specifies said radix includes means for setting said analog input signal to said reference voltage level and adjusting said value in said radix register so that said digital output signal assumes a value that is substantially equal to said reference value.

Claim 49

An algorithmic converter system comprising: an algorithmic converter having a loop gain for converting an analog input signal to a digital code; and a digital computation unit for converting said digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said digital code specifying coefficients of said polynomial; wherein said digital computation unit includes a radix register for storing a value that specifies said radix, and means for determining said value that specifies said radix so that said digital output has a reference value when said analog input is at a reference voltage level; wherein said digital computation unit further includes an offset register for storing an offset value specifying a constant coefficient for said polynomial, and means for computing said offset value so that said digital output has a value of substantially zero when said analog input is at a zero voltage level; and wherein said means for determining said offset value includes means for setting said analog input signal to said zero voltage level and operating said algorithmic converter and said digital computation unit to convert said zero voltage level to said offset value, and said means for determining said value that specifies said radix includes means for setting said analog input signal to said reference voltage level and adjusting said value in said radix register so that said digital output signal assumes a value that is substantially equal to said reference value.

Claim 50

An algorithmic converter system comprising: an algorithmic converter having a loop gain for converting an analog input signal to a digital code; and a digital computation unit for converting said digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said digital code specifying coefficients of said polynomial; wherein said digital computation unit includes a radix register for storing a value that specifies said radix, and means for determining said value that specifies said radix so that said digital output has a reference value when said analog input is at a reference voltage level; and wherein said digital computation unit includes a multiplier connected to said radix register for computing powers of said radix, a power table memory connected to said multiplier for storing the powers of said radix computed by said multiplier, an accumulator register, and an adder/subtractor unit; and said adder/subtractor unit has an output coupled to said accumulator register for loading a result of said adder/subtractor unit in said accumulator register, a first input coupled to said accumulator register for receiving a previous result having been loaded into said accumulator register, a second input coupled to said power table memory for receiving a power of said radix from said power table memory, and a control input responsive to said digital code for operating said adder/subtractor as either an adder or a subtractor for computing said polynomial.

Claim 51

An algorithmic converter system comprising: an algorithmic converter having a loop gain for converting an analog input signal to a digital code; and a digital computation unit for converting said digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said digital code specifying coefficients of said polynomial; wherein said digital computation unit includes a radix register for storing a value that specifies said radix, and means for determining said value that specifies said radix so that said digital output has a reference value when said analog input is at a reference voltage level; and wherein said digital computation unit includes a multiplier connected to said radix register for computing powers of said radix, a power table memory connected to said multiplier for storing the powers of said radix computed by said multiplier, an accumulator register, and an adder/subtractor unit; and said adder/subtractor unit has an output coupled to said accumulator register for loading a result of said adder/subtractor unit in said accumulator register, a first input coupled to said accumulator register for receiving a previous result having been loaded into said accumulator register, a second input coupled to said power table memory for receiving a power of said radix from said power table memory, and a control input responsive to said digital code for operating said adder/subtractor as either an adder or a subtractor for computing said polynomial.

Claim 52

An algorithmic converter system comprising: an algorithmic converter having a loop gain for converting an analog input signal to a digital code; and a digital computation unit for converting said digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said digital code specifying coefficients of said polynomial; wherein said digital computation unit includes an offset register for storing an offset value specifying a constant coefficient for said polynomial, and means for computing said offset value by setting said analog input signal to a first reference voltage and operating said algorithmic converter and said computational unit for converting said analog input signal to a first digital value and computing said offset value as a difference between said first digital value and a first reference value; and wherein said digital computation unit includes a radix register for storing a value that specifies said radix, and means for determining said value that specifies said radix by setting said analog input signal to a second reference voltage and operating said algorithmic converter and said computational unit for converting said analog input signal to a second digital value, comparing said second digital value to said second reference value, and in response to the comparing of said second digital value to said second reference value, adjusting said value that specifies said radix so that said analog input signal is converted by said algorithmic converter and said computational unit to a digital value approximately equal to said second reference value.

Claim 53

An algorithmic converter system comprising: an algorithmic converter having a loop gain for converting an analog input signal to a digital code; and a digital computation unit for converting said digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said digital code specifying coefficients of said polynomial; wherein said digital computation unit includes an offset register for storing an offset value specifying a constant coefficient for said polynomial, and means for computing said offset value by setting said analog input signal to a first reference voltage and operating said algorithmic converter and said computational unit for converting said analog input signal to a first digital value and computing said offset value as a difference between said first digital value and a first reference value; and wherein said digital computation unit includes a radix register for storing a value that specifies said radix, and means for determining said value that specifies said radix by setting said analog input signal to a second reference voltage and operating said algorithmic converter and said computational unit for converting said analog input signal to a second digital value, comparing said second digital value to said second reference value, and in response to the comparing of said second digital value to said second reference value, adjusting said value that specifies said radix so that said analog input signal is converted by said algorithmic converter and said computational unit to a digital value approximately equal to said second reference value.

Claim 54

The algorithmic converter system as claimed in claim 37, wherein said reference values are positive and negative binary numbers having substantially the same magnitude.

Claim 55

The algorithmic converter system as claimed in claim 38, wherein said reference values are a positive full scale value and a negative full scale value.

Claim 56

The algorithmic converter system as claimed in claim 37, further comprising means for alternately operating said means for computing said offset value and said means for determining said value that specifies said radix so that each of said means for computing said offset value and said means for determining said value that specifies said radix is each operated a plurality of times in succession to determine a single offset value and a single value that specifies said radix for use in a normal conversion mode.

Claim 57

An algorithmic converter system comprising: an algorithmic converter having a loop gain for converting an analog input signal to a digital code; and a digital computation unit for converting said digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said digital code specifying coefficients of said polynomial, wherein said digital computation unit includes a successive-approximation register for storing a value that specifies said radix, an offset register for storing an offset value specifying a constant coefficient for said polynomial, an analog multiplexer for setting said analog input signal to a zero voltage level or to a reference voltage level, a numerical comparator for comparing said digital output signal to a reference value, and a calibration controller operative in a calibration mode for controlling said analog multiplexer to set said analog input signal to said zero voltage level and to load in said offset register a digital output signal computed by said computation unit from digital code converted by said algorithmic converter when said analog input signal is set to said zero voltage level, and then to control said analog multiplexer to set said analog input signal to said reference voltage level and to successively adjust bits in said successive approximation register in response to said numerical comparator.

Claim 58

An algorithmic converter system comprising: an algorithmic converter having a loop gain for converting an analog input signal to a digital code; and a digital computation unit for converting said digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said digital code specifying coefficients of said polynomial, wherein said digital computation unit includes a successive-approximation register for storing a value that specifies said radix, an offset register for storing an offset value specifying a constant coefficient for said polynomial, an analog multiplexer for setting said analog input signal to a zero voltage level or to a reference voltage level, a numerical comparator for comparing said digital output signal to a reference value, and a calibration controller operative in a calibration mode for controlling said analog multiplexer to set said analog input signal to said zero voltage level and to load in said offset register a digital output signal computed by said computation unit from digital code converted by said algorithmic converter when said analog input signal is set to said zero voltage level, and then to control said analog multiplexer to set said analog input signal to said reference voltage level and to successively adjust bits in said successive approximation register in response to said numerical comparator.

Claim 59

The algorithmic converter system as claimed in claim 41, wherein said reference value is a full-scale value of said digital output signal.

Claim 60

The algorithmic converter system as claimed in claim 41, wherein said algorithmic converter is a redundant signed digit (RSD) algorithmic converter so that said digital code is a three-state code, and each of said coefficients of said polynomial specified by said three-state code has either a first value when a corresponding digit of said three-state code has a first state or a second value when the corresponding digit of said three-state code has a second state or a third value when the corresponding digit of said three-state code has a third state.

Claim 61

The algorithmic converter system as claimed in claim 41, wherein said digital computation unit includes a multiplier connected to said register for computing powers of said radix, a power table memory connected to said multiplier for storing the powers of said radix computed by said multiplier, an accumulator register, and an adder/subtractor unit, and a multiplexer; said multiplexer has a first data input coupled to said offset register for receiving the offset value from said offset register and a second data input connected to said accumulator register to receive a data value from said accumulator register, and a data output providing a selected value; and said adder/subtractor unit has an output coupled to said accumulator register for loading a result of said adder/subtractor unit in said accumulator register, a first input coupled to said data output of said multiplexer for receiving the selected value, a second input coupled to said power table memory for receiving a power of said radix from said power table memory, and a control input responsive to said digital code for operating said adder/subtractor as either an adder or a subtractor for computing said polynomial.

Claim 62

An algorithmic converter system comprising: an algorithmic converter having a loop gain substantially less than two for converting an analog input signal to a redundant binary digital code; and a digital computation unit for converting said redundant digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said redundant digital code specifying coefficients of said polynomial, wherein each of said coefficients of said polynomial specified by said redundant binary code has either a first value when the corresponding bit of said redundant binary code has a first binary state or a second value when a corresponding bit of said binary code has a second binary state; wherein said digital computation unit includes a successive-approximation register for storing a value that specifies said radix, an offset register for initially storing a first reference value and for storing at a later time an offset value specifying a constant coefficient for said polynomial, an analog multiplexer for setting said analog input signal to a first reference voltage or to a second reference voltage, a numerical comparator for comparing said digital output signal to a second reference value, and a calibration controller operative in a calibration mode for controlling a plurality of successive iterations, each iteration including: a) controlling said analog multiplexer to set said analog input signal to said first reference voltage and to control said computational unit to initially load in said offset register said first reference value, and to use said first reference value as a constant coefficient of said polynomial during computation of said offset value from redundant digital code converted by said redundant algorithmic converter when said analog input signal is set to said first voltage level, and to load said offset value in said offset register, and then b) controlling said analog multiplexer to set said analog input signal to said reference voltage level and to adjust selected bits in said successive approximation register in response to said numerical comparator during computation of said digital output signal from redundant digital code converted by said redundant algorithmic converter when said analog input signal is set to said second reference value so that said digital output signal is driven toward said second reference value when said analog input is set to said reference voltage level, so that after said plurality of successive iterations, when said analog input is at said first reference voltage, said digital output is approximately equal to said first reference value, and when said analog input is at said second reference voltage, said digital output is approximately equal to said second reference value.

Claim 63

An algorithmic converter system comprising: an algorithmic converter having a loop gain substantially less than two for converting an analog input signal to a redundant binary digital code; and a digital computation unit for converting said redundant digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to said loop gain, said redundant digital code specifying coefficients of said polynomial, wherein each of said coefficients of said polynomial specified by said redundant binary code has either a first value when the corresponding bit of said redundant binary code has a first binary state or a second value when a corresponding bit of said binary code has a second binary state; wherein said digital computation unit includes a successive-approximation register for storing a value that specifies said radix, an offset register for initially storing a first reference value and for storing at a later time an offset value specifying a constant coefficient for said polynomial, an analog multiplexer for setting said analog input signal to a first reference voltage or to a second reference voltage, a numerical comparator for comparing said digital output signal to a second reference value, and a calibration controller operative in a calibration mode for controlling a plurality of successive iterations, each iteration including: a) controlling said analog multiplexer to set said analog input signal to said first reference voltage and to control said computational unit to initially load in said offset register said first reference value, and to use said first reference value as a constant coefficient of said polynomial during computation of said offset value from redundant digital code converted by said redundant algorithmic converter when said analog input signal is set to said first voltage level, and to load said offset value in said offset register, and then b) controlling said analog multiplexer to set said analog input signal to said reference voltage level and to adjust selected bits in said successive approximation register in response to said numerical comparator during computation of said digital output signal from redundant digital code converted by said redundant algorithmic converter when said analog input signal is set to said second reference value so that said digital output signal is driven toward said second reference value when said analog input is set to said reference voltage level, so that after said plurality of successive iterations, when said analog input is at said first reference voltage, said digital output is approximately equal to said first reference value, and when said analog input is at said second reference voltage, said digital output is approximately equal to said second reference value.

Claim 64

The algorithmic converter system as claimed in claim 45, wherein said reference values are positive and negative binary numbers having substantially the same magnitude.

Claim 65

The algorithmic converter system as claimed in claim 45, wherein said reference values are a positive full scale value and a negative full scale value.

Claim 66

The algorithmic converter system as claimed in claim 45, wherein said digital computation unit includes a multiplier connected to said register for computing powers of said radix, a power table memory connected to said multiplier for storing the powers of said radix computed by said multiplier, an accumulator register, and an adder/subtractor unit, and a multiplexer; said multiplexer has a first data input coupled to said offset register for receiving the offset value from said offset register and a second data input connected to said accumulator register to receive a data value from said accumulator register, and a data output providing a selected value; and said adder/subtractor unit has an output coupled to said accumulator register for loading a result of said adder/subtractor unit in said accumulator register, a first input coupled to said data output of said multiplexer for receiving the selected value, a second input coupled to said power table memory for receiving a power of said radix from said power table memory, and a control input responsive to said redundant binary code for operating said adder/subtractor as either an adder or a subtractor for computing said polynomial.