Peer to peer network for a mobile radio transceiver

Claim 2

A communications systems comprising: plural controllers each controller having a microprocessor, memory, and an asynchronous receiver-transmitter connected by a parallel bus; a serial bus including a serial transmit line, a serial receive line, a single request line, each of the controllers being connected to the transmit and receive lines by way of the asynchronous receiver-transmitter for asynchronous data communications with other controllers; wherein all of the controllers monitor the single request line to detect availability of the serial bus and each controller seizes control of the serial bus independently of the other controllers and serially transmits data over the serial transmit line using only the single request line.

Claim 3

The system according to claim 1, wherein the asynchronous receiver-transmitter is a conventional universal asynchronous receiver-transmitter (UART).

Claim 4

The system according to claim 1, each controller further comprising: a transceiver connected between the asynchronous receiver-transmitter and the transmit and receive lines of the serial bus for converting binary data signals from the asynchronous receiver-transmitter into differential voltage format for transmission over the serial bus to other controllers and converting differential voltage signals received by the controller into binary data signals.

Claim 5

The system according to claim 3, wherein the transceiver is a conventional RS-485 transceiver.

Claim 6

The system according to claim 3, wherein each controller sets the transceiver in one of a transmit mode and a receive mode by changing a logic state of a control output from a port of the controller.

Claim 7

A communications system comprising: plural controllers each controller having a microprocessor, memory, and an asynchronous receiver-transmitter connected by a parallel bars; a serial bus including a transmit line, a receive line, a single request line, each of the controllers being connected to the transmit and receive lines by way of the asynchronous receiver-transmitter for asynchronous data communications with other controllers; wherein all of the controllers monitor the single request line to detect availability of the serial bus and each controller seizes control of the serial bus independently of the other controllers using the single request line and serially transmits data over the serial transmit line; and wherein each controller has a unique address so that a controller having control of the serial bus may directly transmit a data message to a particular controller by including the particular controller's address in the data message, each controller further comprising: means for detecting whether a receive message address coincides with the controller's unique address; means for determining if the received message is free of errors; and means for transmitting an acknowledgment signal over the transmit line to the controller that initiated the message to acknowledge that the message was received without seizing control of the serial bus.

Claim 8

A communications system comprising: plural controllers each controller having a microprocessor, memory, and an asynchronous receiver-transmitter connected by a parallel bars; a serial bus including a transmit line, a receive line, a single request line, each of the controllers being connected to the transmit and receive lines by way of the asynchronous receiver-transmitter for asynchronous data communications with other controllers; wherein all of the controllers monitor the single request line to detect availability of the serial bus and each controller seizes control of the serial bus independently of the other controllers using the single request line and serially transmits data over the serial transmit line; and wherein each controller has a unique address so that a controller having control of the serial bus may directly transmit a data message to a particular controller by including the particular controller's address in the data message, each controller further comprising: means for detecting whether a receive message address coincides with the controller's unique address; means for determining if the received message is free of errors; and means for transmitting an acknowledgment signal over the transmit line to the controller that initiated the message to acknowledge that the message was received without seizing control of the serial bus.

Claim 9

The system according to claim 6, wherein the initiating controller includes an acknowledgement timer which times out a preset time period after the message is sent to the particular controller unless the acknowledgement signal is received before the acknowledgement timer times out.

Claim 10

A communications system comprising: plural controllers each controller having a microprocessor, memory, and an asynchronous receiver-transmitter connected by a parallel bus; a serial bus including transmit, receive, and request lines, each of the controllers being connected to the transmit and receive lines by way of the asynchronous receiver-transmitter for asynchronous data communications with other controllers; wherein each controller monitors the status of the serial bus and seizes control of the serial bus using a request line, wherein each controller has a unique address so that a controller having control of the serial bus may direct data messages to a particular controller by including the particular controller's address in the message, each controller further comprising: means for detecting whether a received message address coincides with the controller's unique address; means for determining if the received message is free of errors; and means for transmitting an acknowledgement signal over the transmit line to the controller that initiated the message was received without seizing control of the serial bus, wherein the initiating controller includes an acknowledgement timer which times out a preset time period after the message is sent to the particular controller unless the acknowledgement signal is received before the acknowledgement timer times out, means for resolving attempts by plural controllers to simultaneously seize the serial bus including a random timer for receiving a randomly determined value after the controller fails to receive an acknowledgement signal before the acknowledgement timer times out, wherein the means for resolving permits the controller to attempt to seize control of the serial bus after the random timer times out.

Claim 11

A communications system comprising: plural controllers each controller having a microprocessor, memory, and an asynchronous receiver-transmitter connected by a parallel bus; a serial bus including transmit, receive, and request lines, each of the controllers being connected to the transmit and receive lines by way of the asynchronous receiver-transmitter for asynchronous data communications with other controllers; wherein each controller monitors the status of the serial bus and seizes control of the serial bus using a request line, wherein each controller has a unique address so that a controller having control of the serial bus may direct data messages to a particular controller by including the particular controller's address in the message, each controller further comprising: means for detecting whether a received message address coincides with the controller's unique address; means for determining if the received message is free of errors; and means for transmitting an acknowledgement signal over the transmit line to the controller that initiated the message was received without seizing control of the serial bus, wherein the initiating controller includes an acknowledgement timer which times out a preset time period after the message is sent to the particular controller unless the acknowledgement signal is received before the acknowledgement timer times out, means for resolving attempts by plural controllers to simultaneously seize the serial bus including a random timer for receiving a randomly determined value after the controller fails to receive an acknowledgement signal before the acknowledgement timer times out, wherein the means for resolving permits the controller to attempt to seize control of the serial bus after the random timer times out.

Claim 12

The system according to claim 8, wherein priority among plural controllers attempting to seize control of the serial bus is established by assigning different randomly determined values to the controllers and wherein a greater randomly determined value provides a lower priority in terms of seizing control of the serial bus.

Claim 13

The system according to claim 2, wherein the conventional UART has a transmit portion that includes a transmit shift register and a transmit latch for converting sequential bytes parallel data transmitted by the microprocessor into a serial format in accordance with a transmit timing generator and a receive portion that includes a receive shift register and a receive latch for converting bytes of serial data into parallel format in accordance with a receive timing generator.

Claim 14

The system according to claim 1, wherein each controller includes a request input port and a request output port connected to the single request line of the serial bus such that when the controller detects an idle state of the single request line at the request input port, the controller transmits a logic signal to the request output port to seize control of the serial bus for transmitting a message over the network.

Claim 15

A peer to peer network, comprising: plural microcontrollers connected as peers over a serial network including a data line and only a single network availability line, each microcontroller selectively receiving and transmitting messages to one or more other microcontrollers using an asynchronous receiver-transmitter, wherein each microcontroller obtains control of the serial network independently of the other microcontrollers and coordinates the transmission of messages over the serial network using logic signals sent to a single microcontroller port connected to the single network availability line.

Claim 16

A peer to peer network, comprising: plural microcontrollers connected as peers over a serial network including a data line and only a single network availability line, each microcontroller selectively receiving and transmitting messages to one or more other microcontrollers using an asynchronous receiver-transmitter, wherein each microcontroller obtains control of the serial network independently of the other microcontrollers and coordinates the transmission of messages over the serial network using logic signals sent to a single microcontroller port connected to the single network availability line.

Claim 17

The peer to peer network, comprising: plural microcontrollers connected as peers over a serial network, each microcontroller selectively receiving and transmitting messages to one or more other microcontrollers using an asynchronous receiver-transmitter having a transmit portion that includes a transmit shift register connected to a transmit latch for converting blocks of parallel data to be transmitted over the network into serial format in accordance with timing control signals provided to the transmit shift register from a transmit timer and a receive portion that includes a receive shift register connected to a receive latch for converting blocks of serial data received from the network into parallel format in accordance with clock signals provided to the receive shift register and the receive latch by a sampling clock, wherein the microcontrollers coordinate direct transmission and reception of messages over the serial network using only one request line on the network.

Claim 18

The peer to peer network, comprising: plural microcontrollers connected as peers over a serial network, each microcontroller selectively receiving and transmitting messages to one or more other microcontrollers using an asynchronous receiver-transmitter having a transmit portion that includes a transmit shift register connected to a transmit latch for converting blocks of parallel data to be transmitted over the network into serial format in accordance with timing control signals provided to the transmit shift register from a transmit timer and a receive portion that includes a receive shift register connected to a receive latch for converting blocks of serial data received from the network into parallel format in accordance with clock signals provided to the receive shift register and the receive latch by a sampling clock, wherein the microcontrollers coordinate direct transmission and reception of messages over the serial network using only one request line on the network.

Claim 19

The peer to peer network according to claim 13, wherein each microcontroller seizes control of the request line to transmit a message over the network and after a predetermined period of time relinquishes control of the request line.

Claim 20

The peer to peer network according to claim 14, wherein after relinquishing control of the request line, each microcontroller sets a corresponding timer with a randomly selected value and waits until the corresponding timer expires before attempting to seize control of the request line.

Claim 23

The method according to claim 16, further comprising: (4) starting an acknowledgement timer at completion of the message transmitted in step (3); (5) relinquishing control of the request line if either the acknowledgement signal is received or the acknowledgement timer times out; and (6) attempting to again seize control of the single request line if the acknowledgement timer times out.

Claim 24

The method according to claim 17, further comprising: after the relinquishing step (5), waiting a random time delay before the attempting step (6).

Claim 25

In a mobile radio communications system providing radio communications between plural mobile stations, each mobile station including a control head connected over a serial bus including a single serial transmit line, a single serial receive line, and a single control line to a mobile transceiver and one or more peripherals, a communication method, comprising coordinating communications between the control head, mobile transceiver, and one or more peripherals in peer to peer fashion with each of the control head, mobile transceiver, and one or more peripherals monitoring and seizing control of the serial bus independently of the others of the control head, mobile transceiver, and one or more peripherals during an idle period using only the single control line in the serial bus and selectively serially transmitting a message over the single serial transmit line in the serial bus.

Claim 26

In a mobile radio communications system providing radio communications between plural mobile stations, each mobile station including a control head connected over a serial bus including a single serial transmit line, a single serial receive line, and a single control line to a mobile transceiver and one or more peripherals, a communication method, comprising coordinating communications between the control head, mobile transceiver, and one or more peripherals in peer to peer fashion with each of the control head, mobile transceiver, and one or more peripherals monitoring and seizing control of the serial bus independently of the others of the control head, mobile transceiver, and one or more peripherals during an idle period using only the single control line in the serial bus and selectively serially transmitting a message over the single serial transmit line in the serial bus.

Claim 27

The system according to claim 19, wherein radio communications between plural mobile stations are trunked and at least some of those communications use a trunked repeater station.

Claim 32

A mobile radio transceiver including: a serial data bus having first and second serial data lines and a single service control line; radio frequency circuitry for transmitting and receiving radio frequency signals via an antenna; a processor for controlling the radio frequency circuitry, said processor being connected to the first and second serial data lines through an asynchronous receiver-transmitter and to the single service control line through an input/output port, wherein when the processor detects an idle state on the service request line through the input/output port, the processor seizes control of the single service control line and transmits a message over the serial bus via the asynchronous receiver-transmitter onto one of the first and second serial data lines using the single service control line, and when the processor detects an active state on the service control line, the processor monitors the other of the first and second serial data lines for messages.

Claim 33

A mobile radio transceiver including: a serial data bus having first and second serial data lines and a single service control line; radio frequency circuitry for transmitting and receiving radio frequency signals via an antenna; a processor for controlling the radio frequency circuitry, said processor being connected to the first and second serial data lines through an asynchronous receiver-transmitter and to the single service control line through an input/output port, wherein when the processor detects an idle state on the service request line through the input/output port, the processor seizes control of the single service control line and transmits a message over the serial bus via the asynchronous receiver-transmitter onto one of the first and second serial data lines using the single service control line, and when the processor detects an active state on the service control line, the processor monitors the other of the first and second serial data lines for messages.

Claim 34

The mobile radio transceiver of claim 23, wherein the asynchronous receiver-transmitter is a conventional universal asynchronous receiver-transmitter.

Claim 35

A mobile radio transceiver including: a control head having a control head microcontroller; a mobile transceiver including radio frequency circuitry for transmitting and receiving radio frequency signals and a mobile transceiver microcontroller; one or more peripherals having a corresponding peripheral microcontroller; a peer to peer serial network connecting the control head, mobile transceiver, and peripheral microcontrollers can communicate with any of the other microcontrollers independently of the other microcontrollers, wherein the peer to peer serial network includes a single serial transmit line and only a single request line by which any one of the control head, mobile transceiver, and peripheral microcontrollers monitor and seize control of the peer to peer network independently of the other microcontrollers in order to serially transmit a message over the single serial transmit line.

Claim 36

A mobile radio transceiver including: a control head having a control head microcontroller; a mobile transceiver including radio frequency circuitry for transmitting and receiving radio frequency signals and a mobile transceiver microcontroller; one or more peripherals having a corresponding peripheral microcontroller; a peer to peer serial network connecting the control head, mobile transceiver, and peripheral microcontrollers can communicate with any of the other microcontrollers independently of the other microcontrollers, wherein the peer to peer serial network includes a single serial transmit line and only a single request line by which any one of the control head, mobile transceiver, and peripheral microcontrollers monitor and seize control of the peer to peer network independently of the other microcontrollers in order to serially transmit a message over the single serial transmit line.

Claim 37

The mobile radio transceiver according to claim 25, wherein the one or more peripherals include an encryption unit, a data terminal, and a vehicular repeater individually connected to the serial data bus.