US5642325A
Expired / Lapsed
US
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Register file read/write cell
Assignee: Philips North America LLC
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Filing: 1995-09-27
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Granted: 1997-06-24
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Expires: 2015-09-27
Abstract
Abstract A cell in a multiport memory is connected to a respective bit line via respective switches. A write enable element is located between the switches and an input of the cell's storage device. A read enable element is located between an output of the storage device and the same switches. Thus, read bit lines and write bit lines are merged and the number of switches per cell is drastically reduced with respect to prior art multiport memories.
Inventors
- 👤 Michael Anthony Ang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:37
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
108 words
An electronic circuit with a multi-port memory that includes a plurality of memory cells, wherein: each cell is coupled to multiple, independently controllable bitlines; each cell comprises: a storage device for storage of a single bit; and multiple switches, each respective one thereof being operative to selectively connect the storage device to a respective one of the bitlines; and each storage device comprises: a write enable element coupled between the multiple switches and an input of the storage device for enabling writing of the cell; and a read enable element coupled between an output of the storage device and the multiple switches for enabling reading of the cell.
Claim 2
Dependent Claim
108 words
An electronic circuit with a multi-port memory that includes a plurality of memory cells, wherein: each cell is coupled to multiple, independently controllable bitlines; each cell comprises: a storage device for storage of a single bit; and multiple switches, each respective one thereof being operative to selectively connect the storage device to a respective one of the bitlines; and each storage device comprises: a write enable element coupled between the multiple switches and an input of the storage device for enabling writing of the cell; and a read enable element coupled between an output of the storage device and the multiple switches for enabling reading of the cell.
Claim 3
Dependent Claim
24 words
The circuit of claim 1, wherein at least the read enable element or the write enable element is rendered operative through a control signal.
Claim 4
Dependent Claim
47 words
The circuit of claim 2, wherein: the storage device comprises a pair of cross-coupled inverters; and the write enable element comprises a write enable transistor having a conduction channel coupled between the multiple switches and the input, and having a control electrode for receiving the control signal.
Claim 5
Dependent Claim
37 words
The circuit of claim 3, wherein: the read enable element comprises a read enable transistor having a conduction channel coupled between the multiple switches and a reference voltage, and having a control electrode coupled to the output.
Claim 6
Dependent Claim
28 words
The circuit of claim 1, wherein the switches are operative to enable simultaneous reading of a specific one of the cells via at least two of the ports.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-23 | 2000-12-23 | 2001-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-23 | 2004-12-23 | 2005-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-23 | 2008-12-23 | 2009-06-24 | $7700.00 | Window Closed / Lapsed |