US5641977A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Compound semiconductor field effect transistor
Assignee: Renesas Electronics Corp
•
Filing: 1995-09-28
•
Granted: 1997-06-24
•
Expires: 2015-09-28
Abstract
Abstract On a semi-insulative GaAs substrate, a n-type GaAs layer, an undoped InGaAs layer, a n + -type GaAs layer are grown in order and a SiO 2 layer is deposited thereon. Subsequently, a photoresist layer having an opening at a gate region is formed. With taking the photoresist layer as a mask, side etching is performed for the SiO 2 layer up to the width corresponding to a recess width. With taking SiO 2 layer as a mask, wet etching is performed for n + -type GaAs layer. The wet etching is further extended to the intermediate depth position of the undoped InGaAs layer. By lift off method employing the photoresist layer, a gate electrode is formed on the center of the bottom of the recess. A source electrode and a drain electrode are also formed. Thus, since the corner portions of the recess is formed of a material (InGaAs) difficult to cause dislocation, the compound semiconductor field effect transistor can prevent degradation of characteristics in high temperature burn-in test.
Inventors
- 👤 Mikio Kanamori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:55
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D30/00; H10D30/80; H10D30/87; H10D30/877; H10D62/00; H10D62/80; H10D62/85
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
145 words
A compound semiconductor field effect transistor comprising: a semi-insulative semiconductor substrate; a first semiconductor layer on said substrate and serving as a channel layer, said first semiconductor layer is an n-type GaAs layer; a second semiconductor layer on said first semiconductor layer and forming corner portions of a recess, said second semiconductor layer being of a material having lower dislocation propagation speed than that of said first semiconductor layer, said second semiconductor layer is undoped InGaAs layer a third semiconductor layer on said second semiconductor layer, said second and third semiconductor layers having a recess extending through said third semiconductor layer and at an intermediate position of said second semiconductor layer; a gate electrode on the bottom surface of said recess; and source and drain electrodes on said third semiconductor layer, said third semiconductor layer forming a contact layer for said source and drain electrodes.
Claim 2
Dependent Claim
145 words
A compound semiconductor field effect transistor comprising: a semi-insulative semiconductor substrate; a first semiconductor layer on said substrate and serving as a channel layer, said first semiconductor layer is an n-type GaAs layer; a second semiconductor layer on said first semiconductor layer and forming corner portions of a recess, said second semiconductor layer being of a material having lower dislocation propagation speed than that of said first semiconductor layer, said second semiconductor layer is undoped InGaAs layer a third semiconductor layer on said second semiconductor layer, said second and third semiconductor layers having a recess extending through said third semiconductor layer and at an intermediate position of said second semiconductor layer; a gate electrode on the bottom surface of said recess; and source and drain electrodes on said third semiconductor layer, said third semiconductor layer forming a contact layer for said source and drain electrodes.
Claim 3
Dependent Claim
175 words
A compound semiconductor field effect transistor comprising: a semi-insulative semiconductor substrate; a first semiconductor layer formed on said substrate and serving as a channel layer; a second semiconductor layer on said first semiconductor layer and forming corner portions of a recess, said second semiconductor layer being formed of a material having lower dislocation propagation speed than that of said first semiconductor layer; a third semiconductor layer on said second semiconductor layer, said second and third semiconductor layers having a first recess with a center portion extending through said third semiconductor layer and at an intermediate position of said second semiconductor layer, and said first and second semiconductor layers having a second recess located at the center portion of said first recess and extending through a remaining portion of said second semiconductor layer and partially recessed in said first semiconductor layer; a gate electrode on the bottom surface of said second recess; and source and drain electrodes on said third semiconductor layer, said third semiconductor layer forming a contact layer for said source and drain electrodes.
Claim 4
Dependent Claim
175 words
A compound semiconductor field effect transistor comprising: a semi-insulative semiconductor substrate; a first semiconductor layer formed on said substrate and serving as a channel layer; a second semiconductor layer on said first semiconductor layer and forming corner portions of a recess, said second semiconductor layer being formed of a material having lower dislocation propagation speed than that of said first semiconductor layer; a third semiconductor layer on said second semiconductor layer, said second and third semiconductor layers having a first recess with a center portion extending through said third semiconductor layer and at an intermediate position of said second semiconductor layer, and said first and second semiconductor layers having a second recess located at the center portion of said first recess and extending through a remaining portion of said second semiconductor layer and partially recessed in said first semiconductor layer; a gate electrode on the bottom surface of said second recess; and source and drain electrodes on said third semiconductor layer, said third semiconductor layer forming a contact layer for said source and drain electrodes.
Claim 5
Dependent Claim
23 words
A compound semiconductor field effect transistor as set forth in claim 1, wherein said third semiconductor layer is n + -type GaAs layer.
Claim 6
Dependent Claim
21 words
A compound semiconductor field effect transistor as set forth in claim 2, wherein said first semiconductor layer is n-type GaAs layer.
Claim 7
Dependent Claim
22 words
A compound semiconductor field effect transistor as set forth in claim 2, wherein said second semiconductor layer is an undoped InGaAs layer.
Claim 8
Dependent Claim
23 words
A compound semiconductor field effect transistor as set forth in claim 2, wherein said third semiconductor layer is n + -type GaAs layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-23 | 2000-12-23 | 2001-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-23 | 2004-12-23 | 2005-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-23 | 2008-12-23 | 2009-06-24 | $7700.00 | Window Closed / Lapsed |