US5636254A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal processing delay circuit
Assignee: Hitachi Ltd
•
Filing: 1995-04-25
•
Granted: 1997-06-03
•
Expires: 2015-04-25
Abstract
Abstract A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.
Inventors
- 👤 Kenichi Hase
- 👤 Ryutaro Horita
- 👤 Kunio Watanabe
- 👤 Yoshiteru Ishida
- 👤 Takashi Nara
- 👤 Hiroshi Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:27
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03H; H03H9/00; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; H03K; H03K5/00; H03K5/13; H03L7/081; H03L7/0812; H03L7/085; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0896; H03L7/099; H03L7/0995; H04; H04L; H04L7/00; H04L7/02; H04L7/0008; H04L7/0016; H04L7/0033; H04L7/0041
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
77 words
A signal processing delay circuit, comprising: first delay means including a first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal; and second delay means including a second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.
Claim 2
Dependent Claim
77 words
A signal processing delay circuit, comprising: first delay means including a first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal; and second delay means including a second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.
Claim 3
Dependent Claim
26 words
A signal processing delay circuit according to claim 1, wherein the first delay means conducts a delay amount control operation according to a closed-loop control operation.
Claim 4
Dependent Claim
57 words
A signal processing delay circuit according to claim 1, wherein: the first delay means includes as the first analog variable delay circuit an oscillation circuit utilizing an analog variable delay line; and the amount of delay of the analog variable line is controlled to synchronize an oscillation output from the oscillation circuit with the external reference signal.
Claim 5
Dependent Claim
69 words
A signal processing delay circuit according to claim 1, wherein: the first delay means includes as the first analog variable delay circuit a phase shifting circuit utilizing an analog variable delay line to pass the external reference signal therethrough; and the amount of delay of the analog variable line is controlled to match a phase of an output from the shifting circuit with that of the external reference signal.
Claim 6
Dependent Claim
48 words
A signal processing delay circuit according to claim 1, further including means for weighting the delay amount control signal generated by the first delay means, wherein the amount of delay of the analog variable delay circuit of the second delay means is controlled by the weighted control signal.
Claim 7
Dependent Claim
38 words
A signal processing delay circuit according to claim 1, wherein the first and second analog variable delay circuits are delay circuits having taps each including a plurality of analog variable delay cells connected in series to each other.
Claim 8
Dependent Claim
31 words
A signal processing delay circuit according to claim 6, wherein the first analog variable delay circuit has a circuit configuration substantially identical to that of the second analog variable delay circuit.
Claim 9
Dependent Claim
72 words
A signal processing delay circuit according to claim 7, wherein the second analog variable delay circuit includes a third analog variable circuit connected in parallel to an input to the second analog variable delay circuit for conducting a synchronous control for an output from the second analog variable delay circuit, thereby obtaining an amount of delay substantially equivalent to half that of a total delay of the second analog variable delay circuit.
Claim 10
Dependent Claim
116 words
A data acquisition circuit for acquiring data in response to a clock signal synchronized with input data thereto, comprising a window adjustment circuit for achieving a phase adjustment between the data and the clock signal, wherein the window adjustment circuit includes a signal processing delay circuit including first delay means including first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.
Claim 11
Dependent Claim
116 words
A data acquisition circuit for acquiring data in response to a clock signal synchronized with input data thereto, comprising a window adjustment circuit for achieving a phase adjustment between the data and the clock signal, wherein the window adjustment circuit includes a signal processing delay circuit including first delay means including first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.
Claim 12
Dependent Claim
21 words
A data acquisition circuit according to claim 9, further including means for creating a clock signal synchronized with the input data.
Claim 13
Dependent Claim
110 words
A data write circuit for writing data on a recording medium, comprising a write pre-compensation circuit for conducting a positional compensation of data according to a data pattern thereof, wherein the write pre-compensation circuit includes a signal processing delay circuit including first delay means including first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.
Claim 14
Dependent Claim
110 words
A data write circuit for writing data on a recording medium, comprising a write pre-compensation circuit for conducting a positional compensation of data according to a data pattern thereof, wherein the write pre-compensation circuit includes a signal processing delay circuit including first delay means including first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.
Claim 15
Dependent Claim
306 words
A signal recording and reproducing system, comprising: a recording medium; a sensor for recording a signal on the recording medium or reproducing a signal from the recording medium; a signal processing circuit for processing a record signal to the sensor or a reproduction signal therefrom; an interface circuit for communicating as data items the processed record and reproduction signals; a processor for controlling operation of the system; a data acquisition circuit for acquiring data in response to a clock signal synchronized with input data thereto, the data acquisition circuit comprising a window adjustment circuit for achieving a phase adjustment between the data and the clock signal, the window adjustment circuit including a signal processing delay circuit including first delay means including a first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including a second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means; and/or a data write circuit for writing data on a recording medium, the data write circuit including a write pre-compensation circuit for conducting a positional compensation of data according to a data pattern of the data, the write pre-compensation circuit including a signal processing delay circuit including first delay means including a first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including a second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.
Claim 16
Dependent Claim
306 words
A signal recording and reproducing system, comprising: a recording medium; a sensor for recording a signal on the recording medium or reproducing a signal from the recording medium; a signal processing circuit for processing a record signal to the sensor or a reproduction signal therefrom; an interface circuit for communicating as data items the processed record and reproduction signals; a processor for controlling operation of the system; a data acquisition circuit for acquiring data in response to a clock signal synchronized with input data thereto, the data acquisition circuit comprising a window adjustment circuit for achieving a phase adjustment between the data and the clock signal, the window adjustment circuit including a signal processing delay circuit including first delay means including a first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including a second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means; and/or a data write circuit for writing data on a recording medium, the data write circuit including a write pre-compensation circuit for conducting a positional compensation of data according to a data pattern of the data, the write pre-compensation circuit including a signal processing delay circuit including first delay means including a first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including a second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.
Claim 17
Dependent Claim
87 words
A signal processing delay circuit, comprising a circuit in a semiconductor chip, wherein the circuit includes first delay means including a first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including a second analog variable delay circuit of which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.
Claim 18
Dependent Claim
87 words
A signal processing delay circuit, comprising a circuit in a semiconductor chip, wherein the circuit includes first delay means including a first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including a second analog variable delay circuit of which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.
Claim 19
Dependent Claim
79 words
A signal processing delay circuit according to claim 13, wherein: the first delay means includes as the first analog variable delay circuit an oscillation circuit utilizing an analog variable delay line and the amount of delay of the analog variable line is controlled to synchronize an oscillation output from the oscillation circuit with the external reference signal, and the first analog variable delay circuit has a circuit configuration substantially identical to that of the second analog variable delay circuit.
Claim 20
Dependent Claim
123 words
A signal processing delay circuit configured in a semiconductor integration circuit, comprising: a first delay means including a first analog variable delay circuit of which an amount of delay is preset according to a stable reference signal and a phase-locked loop circuit for controlling the preset amount of delay, first delay means producing a delay amount control signal; and a second delay means including a second analog delay circuit for conducting, according to the delay amount control signal from the first delay means, a fine control operation of an amount of delay for an input signal as an object of processing, wherein the first analog variable delay circuit has a circuit configuration substantially identical to that of the second analog variable delay circuit.
Claim 21
Dependent Claim
123 words
A signal processing delay circuit configured in a semiconductor integration circuit, comprising: a first delay means including a first analog variable delay circuit of which an amount of delay is preset according to a stable reference signal and a phase-locked loop circuit for controlling the preset amount of delay, first delay means producing a delay amount control signal; and a second delay means including a second analog delay circuit for conducting, according to the delay amount control signal from the first delay means, a fine control operation of an amount of delay for an input signal as an object of processing, wherein the first analog variable delay circuit has a circuit configuration substantially identical to that of the second analog variable delay circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-02 | 2000-12-02 | 2001-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-02 | 2004-12-02 | 2005-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-02 | 2008-12-02 | 2009-06-03 | $7700.00 | Window Closed / Lapsed |