Computer processing unit employing a separate millicode branch history table

Claim 2

In a computer processing system having memory mapped into at least a first and second region, said first region storing instructions belonging to a first instruction set architecture of said computer processing system and said second region storing instructions belonging to a second instruction set architecture of said computer processing system, wherein said first instruction set architecture includes at least one instruction that does not belong to said second instruction set architecture, wherein said at least one instruction belonging to said first instruction set architecture is implemented by a plurality of instructions belonging to said second instruction set architecture, and wherein said instructions belonging to said first instruction set architecture comprise at least one branch type instruction and said instructions belonging to said second instruction set architecture comprise at least one branch type instruction, a method of fetching instructions from said first and second regions of memory into an instruction buffer for execution by a processor unit, the method comprising the steps of: in a first mode, fetching instructions belonging to said first instruction set architecture from said first region of memory into said instruction buffer according to data stored in a first branch history table associated with instructions belonging to said first instruction set architecture; and in a second mode, fetching instructions belonging to said second instruction set architecture from said second region of memory into said instruction buffer according to data stored in a second branch history table associated with instructions belonging to said second instruction set architecture; wherein said second branch history table is separate from said first branch history table.

Claim 3

The method of claim 1, wherein in said second mode, the step of fetching instructions belonging to said second instruction set architecture from said second region of memory into said instruction buffer is controlled according to static condition data generated in said first mode and said data stored in said second branch history table.

Claim 4

The method of claim 1, further comprising the steps of: initializing said computer processing system to operate in said first mode; and switching operation of said computer processing system to said second mode upon said processor unit detecting that an instruction being executed is defined by one or more of said instructions stored in said second region of memory.

Claim 5

The method of claim 3, further comprising the step of: switching operation of said computer processing system back to said first mode upon detecting that an instruction being executed is a predetermined instruction belonging to said second instruction set architecture.

Claim 6

The method of claim 1, wherein addresses of instructions belonging to said second set architecture instruction stored in said second memory are predetermined, and wherein at least one branch type instruction belonging to said second instruction set architecture is removed from said second memory and folded into said second branch history table.

Claim 7

The method of claim 5, wherein all branch type instructions belonging to said second set architecture instruction are removed from said second memory and folded into said second branch history table.

Claim 8

The method of claim 5, wherein said branch type instructions belonging to said second set architecture instruction are classified as one of a first category of branch type instructions and a second category of branch type instructions, wherein said first category of branch type instructions are removed from said second memory and folded into said second branch history table.

Claim 9

The method of claim 7, wherein said first category of branch type instructions belonging to said second instruction set architecture are branch type instructions that depend upon static condition data generated in said first mode.

Claim 10

The method of claim 8, wherein said second instruction set architecture comprise millicode instructions.

Claim 11

The method of claim 5, wherein said second branch history table comprises at least one entry corresponding to said at least one branch type instruction belonging to said second instruction set architecture that is removed from said second memory and folded into said second branch history table, said entry including an address tag, a target address and a condition field, wherein when said second branch history table is accessed with an instruction address matching said address tag, said second branch history table outputs signals to control fetching of one or more instructions located at said target address within said second memory if conditions defined by said condition field are satisfied.

Claim 12

The method of claim 1, wherein said first instruction set architecture comprise system level instructions and said second instruction set architecture comprise millicode instructions.

Claim 13

The method of claim 11, wherein one or more of said millicode instructions define a complex system level instruction.

Claim 14

The method of claim 11, wherein said millicode instructions emulate a third instruction set architecture.

Claim 15

The method of claim 1, wherein said second branch history table associated with said second instruction set architecture comprises an array of entries each corresponding to a branch type instruction stored in said second region of memory.

Claim 16

The method of claim 14, wherein said entries are initialized at initial program load.

Claim 17

The method of claim 14, further comprising the step of: generating static condition data in said first mode, wherein in said second mode, the step of fetching instructions belonging to said second instruction set architecture from said second region of memory into said instruction buffer is controlled according to said static condition data and said data stored in a second branch history table.

Claim 18

A computer processing system comprising: a memory mapped into at least a first and second region, said first region storing instructions belonging to a first instruction set architecture, and said second region storing instructions belonging to a second instruction set architecture of said computer unit, wherein said first instruction set architecture includes at least one instruction that does not belong to said second instruction set architecture, wherein said at least one instruction belonging to said first instruction set architecture is implemented by a plurality of instructions belonging to said second instruction set architecture, and wherein said instructions belonging to said first instruction set architecture comprise at least one branch type instruction and said instructions belonging to said second instruction set architecture comprise at least one branch type instruction; an instruction buffer, coupled to said memory, for storing instructions that are executed by a processor unit; means for fetching instructions belonging to said first instruction set architecture from said first region of memory into said instruction buffer according to data stored in a first branch history table associated with instructions belonging to said first instruction set architecture in a first mode; and means for fetching instructions belonging to said second instruction set architecture from said second region of memory into said instruction buffer according to data stored in a second branch history table associated with instructions belonging to said second instruction set architecture in a second mode; wherein said second branch history table is separate from said first branch history table.

Claim 19

A computer processing system comprising: a memory mapped into at least a first and second region, said first region storing instructions belonging to a first instruction set architecture, and said second region storing instructions belonging to a second instruction set architecture of said computer unit, wherein said first instruction set architecture includes at least one instruction that does not belong to said second instruction set architecture, wherein said at least one instruction belonging to said first instruction set architecture is implemented by a plurality of instructions belonging to said second instruction set architecture, and wherein said instructions belonging to said first instruction set architecture comprise at least one branch type instruction and said instructions belonging to said second instruction set architecture comprise at least one branch type instruction; an instruction buffer, coupled to said memory, for storing instructions that are executed by a processor unit; means for fetching instructions belonging to said first instruction set architecture from said first region of memory into said instruction buffer according to data stored in a first branch history table associated with instructions belonging to said first instruction set architecture in a first mode; and means for fetching instructions belonging to said second instruction set architecture from said second region of memory into said instruction buffer according to data stored in a second branch history table associated with instructions belonging to said second instruction set architecture in a second mode; wherein said second branch history table is separate from said first branch history table.

Claim 20

The computer processing system of claim 17, wherein said means for fetching instructions belonging to said second instruction set architecture from said second region of memory into said instruction buffer is controlled according to static condition data generated in said first mode and said data stored in said second branch history table.

Claim 21

The computer processing system of claim 17, wherein said computer system is initialized to operate in said first mode, further comprising logic that switches operation to said second mode upon detecting that an instruction being executed by said processor unit is defined by one or more of said instructions stored in said second memory.

Claim 22

The computer processing system of claim 19, further comprising logic that switches operation of said computer processing system back to said first mode upon detecting that an instruction being executed by said processor unit is a predetermined instruction belonging to said second set of instructions.

Claim 23

The computer processing system of claim 17, wherein addresses of instructions belonging to said second instruction set architecture stored in said second memory are predetermined, and wherein at least one branch type instruction belonging to said second instruction set architecture is removed from said second memory and folded into said second branch history table.

Claim 24

The computer processing system of claim 21, wherein all branch type instructions belonging to said second instructure set architecture are removed from said second memory and folded into said second branch history table.

Claim 25

The computer processing system of claim 21, wherein said branch type instructions belonging to said second instructure set architecture are classified as one of a first category of branch type instructions and a second category of branch type instructions, wherein said first category of branch type instructions are removed from said second memory and folded into said second branch history table.

Claim 26

The computer processing system of claim 23, wherein said first category of branch type instructions belonging to said second instructure set architecture are branch type instructions that depend upon static condition data generated in said first mode.

Claim 27

The computer processing system of claim 24, wherein said second instruction set architecture comprise millicode instructions.

Claim 28

The computer processing system of claim 21, wherein said second branch history table comprises at least one entry corresponding to said at least one branch type instruction belonging to said second instructure set architecture that is removed from said second memory and folded into said second branch history table, said entry including an address tag, a target address and a condition field, wherein when said second branch history table is accessed with an instruction address matching said address tag, said second branch history table outputs signals to control fetching of one or more instructions located at said target address within said second memory if conditions defined by said condition field are satisfied.

Claim 29

The computer processing system of claim 17, wherein said first instruction set comprise system level instructions and said second instructure set architecture comprise millicode instructions.

Claim 30

The computer processing system of claim 27, wherein one or more of said millicode instructions define a complex system level instruction.

Claim 31

The computer processing system of claim 27, wherein said millicode instructions emulate a third instruction set architecture.

Claim 32

The computer processing system of claim 17, wherein said second branch history table associated with said second instruction set architecture comprises an array of entries each corresponding to a branch type instruction stored in said second region of memory.

Claim 33

The computer processing system of claim 30, wherein said entries are initialized at initial program load.

Claim 34

The computer processing system of claim 30, further comprising: an instruction decoder, coupled to said instruction buffer, that generates static condition data in said first mode, wherein said second branch history table associated with said second set of instructions further comprises logic that outputs signals to control fetching of instructions located at one of a target address and a next sequential address within said second memory according to said static condition data.

Claim 35

A computer processing unit comprising: a memory mapped into at least a first and second regions, said first region storing instructions belonging to a first instruction set architecture of said computer processing unit, and said second region storing instructions belonging to a second instruction set architecture of said computer processing system, wherein said first instruction set architecture includes at least one instruction that does not belong to said second instruction set architecture, wherein said at least one instruction belonging to said first instruction set architecture is implemented by a plurality of instructions belonging to said second instruction set architecture, and wherein said instructions belonging to said first instruction set architecture comprise at least one branch type instruction and said instructions belonging to said second instruction set architecture comprise at least one branch type instruction; an instruction buffer, coupled to said memory, for storing instructions that are executed by a processor unit; an instruction address register for storing an address of at least one instruction fetched from said memory into said instruction buffer; a first branch history table that, in a first mode, controls a multiplexer to load one of a target address and a next sequential address of an instruction belonging to said first instruction set architecture into said instruction address register in a second fetching cycle according to said address stored in said instruction address register in a first fetching cycle, wherein said second fetching cycle is subsequent to said first fetching cycle; and a second branch history table that, in a second mode, controls said multiplexer to load one of a target address and a next sequential address of an instruction belonging to said second instruction set architecture into said instruction address register in a fourth fetching cycle according to said address stored in said instruction address register in a third fetching cycle, wherein said fourth fetching cycle is subsequent to said third fetching cycle; wherein said second branch history table is separated from said first branch history table.

Claim 36

A computer processing unit comprising: a memory mapped into at least a first and second regions, said first region storing instructions belonging to a first instruction set architecture of said computer processing unit, and said second region storing instructions belonging to a second instruction set architecture of said computer processing system, wherein said first instruction set architecture includes at least one instruction that does not belong to said second instruction set architecture, wherein said at least one instruction belonging to said first instruction set architecture is implemented by a plurality of instructions belonging to said second instruction set architecture, and wherein said instructions belonging to said first instruction set architecture comprise at least one branch type instruction and said instructions belonging to said second instruction set architecture comprise at least one branch type instruction; an instruction buffer, coupled to said memory, for storing instructions that are executed by a processor unit; an instruction address register for storing an address of at least one instruction fetched from said memory into said instruction buffer; a first branch history table that, in a first mode, controls a multiplexer to load one of a target address and a next sequential address of an instruction belonging to said first instruction set architecture into said instruction address register in a second fetching cycle according to said address stored in said instruction address register in a first fetching cycle, wherein said second fetching cycle is subsequent to said first fetching cycle; and a second branch history table that, in a second mode, controls said multiplexer to load one of a target address and a next sequential address of an instruction belonging to said second instruction set architecture into said instruction address register in a fourth fetching cycle according to said address stored in said instruction address register in a third fetching cycle, wherein said fourth fetching cycle is subsequent to said third fetching cycle; wherein said second branch history table is separated from said first branch history table.

Claim 37

The computer processing unit of claim 33, further comprising: an instruction decoder, coupled to said instruction buffer, that generates static condition data in said first mode, wherein said second branch history table comprises logic that evaluates said static condition data to determine whether to control said multiplexer to load one of said target address and said next sequential address.

Claim 38

The computer processing unit of claim 33, wherein said first instruction set architecture comprise system level instructions and said second instruction set architecture comprise millicode instructions.

Claim 39

The computer processing unit of claim 35, wherein addresses of said millicode instructions stored in said second memory are predetermined, and wherein at least one branch type millicode instruction is removed from said second memory and folded into said second table.

Claim 40

The computer processing unit of claim 36, wherein all branch type millicode instructions are removed from said second memory and folded into said second table.

Claim 41

The computer processing unit of claim 36, wherein said branch type millicode instructions are classified as one of a first category of branch type millicode instructions and a second category of branch type millicode instructions, wherein said first category of branch type millicode instructions are removed from said second memory and folded into said second table.

Claim 42

The computer processing unit of claim 36, wherein said first category of branch type millicode instructions are branch type instructions that depend upon static condition data generated in said first mode.

Claim 43

The computer processing unit of claim 36, wherein said second table comprises at least one entry corresponding to at least one branch type millicode instruction that is removed from said second memory and folded into said second table, said entry including an address tag, a target address and a condition field, wherein when said second table is accessed with an instruction address matching said address tag, said second table outputs signals to control fetching of one or more instructions located at said target address within said second memory if conditions defined by said condition field are satisfied.