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US5633525A Expired / Lapsed US ⏱️ 0.0 years remaining

Lateral field effect transistor

Assignee: Fuji Electric Co Ltd
•
Filing: 1995-11-01
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Granted: 1997-05-27
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Expires: 2015-11-01
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Abstract

Abstract A lateral field effect transistor includes a semiconductor substrate, a source region further with source region stripes formed on the semiconductor substrate, and a drain region with drain region stripes formed on the semiconductor substrate and spaced laterally from the source region stripes. In addition, the lateral field effect transistor includes a source electrode having a first source electrode layer connected to the source region via a source contact and a second source electrode layer straddling the source region stripes and the drain region stripes. The first source electrode layer and the second source electrode layer are separated by an inter-layer insulation film and connected via a source connection hole formed through the inter-layer insulation film. In addition, the lateral field effect transistor includes a drain electrode having a first drain electrode layer connected to the drain region via a drain contact and a second drain electrode layer straddling the source region stripes and the drain region stripes. The first drain electrode layer and the second drain electrode layer are separated by an inter-layer insulation film and connected via a drain connection hole formed through the inter-layer insulation film. The lateral field effect transistor also includes a source pad disposed on the second source electrode layer and a drain pad disposed on the second drain electrode layer.

Inventors

  • 👤 Akio Kitamura
  • 👤 Naoto Fujishima

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 14:34
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/603; H10D30/605; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/257; H10W; H10W20/00; H10W20/40; H10W20/482; H10W20/484; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D64/111; H10W72/00; H10W72/90; H10W72/951

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 180 words
A lateral field effect transistor comprising: a semiconductor substrate; a source region comprising source region stripes formed on said semiconductor substrate; a drain region comprising drain region stripes formed on said semiconductor substrate and spaced laterally from said source region stripes; a source electrode comprising a first source electrode layer connected to said source region via at least one source contact and a second source electrode layer straddling said source region stripes and said drain region stripes, said first source electrode layer and said second source electrode layer being separated by an inter-layer insulation film and connected via at least one source connection hole formed through said inter-layer insulation film; and a drain electrode comprising a first drain electrode layer connected to said drain region via at least one drain contact and a second drain electrode layer straddling said source region stripes and said drain region stripes, said first drain electrode layer and said second drain electrode layer being separated by an inter-layer insulation film and connected via at least one drain connection hole formed through said inter-layer insulation film.
Claim 2
Dependent Claim 180 words
A lateral field effect transistor comprising: a semiconductor substrate; a source region comprising source region stripes formed on said semiconductor substrate; a drain region comprising drain region stripes formed on said semiconductor substrate and spaced laterally from said source region stripes; a source electrode comprising a first source electrode layer connected to said source region via at least one source contact and a second source electrode layer straddling said source region stripes and said drain region stripes, said first source electrode layer and said second source electrode layer being separated by an inter-layer insulation film and connected via at least one source connection hole formed through said inter-layer insulation film; and a drain electrode comprising a first drain electrode layer connected to said drain region via at least one drain contact and a second drain electrode layer straddling said source region stripes and said drain region stripes, said first drain electrode layer and said second drain electrode layer being separated by an inter-layer insulation film and connected via at least one drain connection hole formed through said inter-layer insulation film.
Claim 3
Dependent Claim 19 words
The lateral field transistor of claim 1, further comprising a source pad disposed on said second source electrode layer.
Claim 4
Dependent Claim 19 words
The lateral field transistor of claim 1, further comprising a drain pad disposed on said second drain electrode layer.
Claim 5
Dependent Claim 40 words
The lateral field effect transistor of claim 1, wherein said at least one source connection hole is formed beneath said second source electrode layer, and said at least one drain connection hole is formed beneath said second drain electrode layer.
Claim 6
Dependent Claim 38 words
The lateral field effect transistor of claim 4, wherein said at least one source connection hole is disposed above said source region stripes, and said at least one drain connection hole is disposed above said drain region stripes.
Claim 7
Dependent Claim 50 words
The lateral field effect transistor of claim 5, wherein said at least one source contact and said at least one source connection hole are displaced laterally from one another, and said at least one drain contact and said at least one drain connection hole are displaced laterally from one another.
Claim 8
Dependent Claim 48 words
The lateral field effect transistor of claim 1, wherein: beneath said second drain electrode layer, said first source electrode layer is wider than said first drain electrode layer, and beneath said second source electrode layer, said first drain electrode layer is wider than said first source electrode layer.

References Cited (Backward Citations)

JPS61144872A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-05-26 2000-11-25 2001-05-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-05-26 2004-11-25 2005-05-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-05-26 2008-11-25 2009-05-27 $7700.00 Window Closed / Lapsed

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