US5631929A
Expired / Lapsed
US
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Electronic transmitter having a digital combiner circuit for transmitting multiple digital input signals simultaneously
Assignee: Unisys Corp
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Filing: 1995-05-09
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Granted: 1997-05-20
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Expires: 2015-05-09
Abstract
Abstract An electronic transmitter transmits multiple digital input signals simultaneously by including an encoding circuit, a digital combiner circuit, and a modulator circuit. The encoding circuit encodes each of the digital input signals as a sequence of "1" and "0" chips with all of the chip sequences being synchronized in parallel; the digital combiner circuit generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in the synchronized chip sequences; and, the modulator circuit generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of the signed multi-bit digital signal.
Inventors
- 👤 Delon K. Jones
- 👤 Steven T. Barham
- 👤 Thomas R. Giallorenzi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:26
CPC Classifications
H; H04; H04J; H04J13/00; H04J13/0007; H04J13/0022; H04B; H04B1/00; H04B1/69; H04B1/707; H04J13/10
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
211 words
An electronic transmitter for transmitting multiple digital input signals simultaneously; comprising: an encoding circuit, which encodes each of said digital input signals and thereby generates a respective sequence of "1" and "0" chips for each input signal, with all of said chip sequences being synchronized in parallel; a digital combiner circuit, coupled to said encoding circuit, that generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in said synchronized chip sequences; said digital combiner circuit including a first digital adder circuit which sums concurrent "1" chips in said synchronized chip sequences, a second digital adder circuit which sums concurrent "0" chips in said synchronized chip sequences, a digital subtracter circuit which subtracts the sum formed by said second adder circuit from the sum formed by said first adder circuit, and a control circuit coupled said second adder circuit which inverts all chips in selected sequences and passes all chips in the remaining sequences prior to their summation by said second adder circuit; and, a modulator circuit, coupled to said digital combiner circuit, which generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of said signed multi-bit digital signal.
Claim 2
Dependent Claim
211 words
An electronic transmitter for transmitting multiple digital input signals simultaneously; comprising: an encoding circuit, which encodes each of said digital input signals and thereby generates a respective sequence of "1" and "0" chips for each input signal, with all of said chip sequences being synchronized in parallel; a digital combiner circuit, coupled to said encoding circuit, that generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in said synchronized chip sequences; said digital combiner circuit including a first digital adder circuit which sums concurrent "1" chips in said synchronized chip sequences, a second digital adder circuit which sums concurrent "0" chips in said synchronized chip sequences, a digital subtracter circuit which subtracts the sum formed by said second adder circuit from the sum formed by said first adder circuit, and a control circuit coupled said second adder circuit which inverts all chips in selected sequences and passes all chips in the remaining sequences prior to their summation by said second adder circuit; and, a modulator circuit, coupled to said digital combiner circuit, which generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of said signed multi-bit digital signal.
Claim 3
Dependent Claim
57 words
An electronic transmitter according to claim 1 wherein said digital combiner circuit further includes a memory circuit coupled to said subtractor circuit which stores multiple linearly scaled products of the difference from said subtractor circuit and which is addressed by said difference concatenated with a digital control signal that indicates the total number of said input signals.
Claim 4
Dependent Claim
186 words
An electronic transmitter for transmitting multiple digital input signals simultaneously; comprising: an encoding circuit, which encodes each of said digital input signals and thereby generates a respective sequence of "1" and "0" chips for each input signal, with all of said chip sequences being synchronized in parallel; a digital combiner circuit, coupled to said encoding circuit, that generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in said synchronized chip sequences; said digital combiner circuit including a digital adder circuit which sums concurrent "1" chips in said synchronized chip sequences, a first digital subtracter circuit which subtracts the sum formed by said adder circuit from the total number of said input signals, and a second digital subtracter circuit which subtracts the difference formed by said first binary subtracter circuit from the sum formed by said adder circuit and, a modulator circuit, coupled to said digital combiner circuit, which generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of said signed multi-bit digital signal.
Claim 5
Dependent Claim
186 words
An electronic transmitter for transmitting multiple digital input signals simultaneously; comprising: an encoding circuit, which encodes each of said digital input signals and thereby generates a respective sequence of "1" and "0" chips for each input signal, with all of said chip sequences being synchronized in parallel; a digital combiner circuit, coupled to said encoding circuit, that generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in said synchronized chip sequences; said digital combiner circuit including a digital adder circuit which sums concurrent "1" chips in said synchronized chip sequences, a first digital subtracter circuit which subtracts the sum formed by said adder circuit from the total number of said input signals, and a second digital subtracter circuit which subtracts the difference formed by said first binary subtracter circuit from the sum formed by said adder circuit and, a modulator circuit, coupled to said digital combiner circuit, which generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of said signed multi-bit digital signal.
Claim 6
Dependent Claim
36 words
An electronic transmitter according to claim 3 wherein said digital combiner circuit further includes a control circuit coupled to said adder circuit which selectively inhibits said "1" chips prior to their summation by said adder circuit.
Claim 7
Dependent Claim
59 words
An electronic transmitter according to claim 3 wherein said digital combiner circuit further includes a memory circuit coupled to said second subtractor circuit which stores multiple linearly scaled products of the difference from said second subtractor circuit and which is addressed by that difference concatenated with a digital control signal that indicates the total number of said input signals.
Claim 8
Dependent Claim
162 words
An electronic transmitter for transmitting multiple digital input signals simultaneously; comprising: an encoding circuit, which encodes each of said digital input signals and thereby generates a respective sequence of "1" and "0" chips for each input signal, with all of said chip sequences being synchronized in parallel; a digital combiner circuit, coupled to said encoding circuit, that generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in said synchronized chip sequences; said digital combiner circuit including a digital adder circuit which sums concurrent "1" chips in said synchronized chip sequences, and a digital subtracter circuit which subtracts the total number of said input signals from twice the sum formed by said adder circuit and, a modulator circuit, coupled to said digital combiner circuit, which generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of said signed multi-bit digital signal.
Claim 9
Dependent Claim
162 words
An electronic transmitter for transmitting multiple digital input signals simultaneously; comprising: an encoding circuit, which encodes each of said digital input signals and thereby generates a respective sequence of "1" and "0" chips for each input signal, with all of said chip sequences being synchronized in parallel; a digital combiner circuit, coupled to said encoding circuit, that generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in said synchronized chip sequences; said digital combiner circuit including a digital adder circuit which sums concurrent "1" chips in said synchronized chip sequences, and a digital subtracter circuit which subtracts the total number of said input signals from twice the sum formed by said adder circuit and, a modulator circuit, coupled to said digital combiner circuit, which generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of said signed multi-bit digital signal.
Claim 10
Dependent Claim
36 words
An electronic transmitter according to claim 6 wherein said digital combiner circuit further includes a control circuit coupled to said adder circuit which selectively inhibits said "1" chips prior to their summation by said adder circuit.
Claim 11
Dependent Claim
58 words
An electronic transmitter according to claim 7 wherein said digital combiner circuit further includes a memory circuit coupled to said subtractor circuit which stores multiple linearly scaled products of the difference from said digital subtractor circuit and which is addressed by said difference concatenated with a digital control signal that indicates the total number of said input signals.
Claim 12
Dependent Claim
194 words
An electronic transmitter for transmitting multiple digital input signals simultaneously; comprising: an encoding circuit, which encodes each of said digital input signals and thereby generates a respective sequence of "1" and "0" chips for each input signal, with all of said chip sequences being synchronized in parallel; a digital combiner circuit, coupled to said encoding circuit, that generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in said synchronized chip sequences; said digital combiner circuit including a digital adder circuit which sums concurrent "1" chips in said synchronized chip sequences, and a memory circuit coupled to said adder circuit which stores linearly scaled products said number of "1" chips minus said number of "0" chips that concurrently occur in said synchronized chip sequences, and which is addressed by said sum concatenated with a digital control signal which indicates the total number of said input signals; and a modulator circuit, coupled to said digital combiner circuit, which generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of said signed multi-bit digital signal.
Claim 13
Dependent Claim
194 words
An electronic transmitter for transmitting multiple digital input signals simultaneously; comprising: an encoding circuit, which encodes each of said digital input signals and thereby generates a respective sequence of "1" and "0" chips for each input signal, with all of said chip sequences being synchronized in parallel; a digital combiner circuit, coupled to said encoding circuit, that generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in said synchronized chip sequences; said digital combiner circuit including a digital adder circuit which sums concurrent "1" chips in said synchronized chip sequences, and a memory circuit coupled to said adder circuit which stores linearly scaled products said number of "1" chips minus said number of "0" chips that concurrently occur in said synchronized chip sequences, and which is addressed by said sum concatenated with a digital control signal which indicates the total number of said input signals; and a modulator circuit, coupled to said digital combiner circuit, which generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of said signed multi-bit digital signal.
Claim 14
Dependent Claim
35 words
An electronic transmitter according to claim 9 wherein said digital combiner circuit includes a control circuit coupled to said adder circuit which selectively inhibits said "1" chips prior to their summation by said adder circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-19 | 2000-11-18 | 2001-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-19 | 2004-11-18 | 2005-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-19 | 2008-11-18 | 2009-05-20 | $7700.00 | Window Closed / Lapsed |