Standard cell having a capacitor and a power supply capacitor for reducing noise and method of formation

Claim 2

An integrated circuit standard cell comprising: a substrate; a first doped substrate region within the substrate and biased to a ground voltage potential via a first metal region, the first doped substrate region having a doped portion of a first conductivity type; a second doped substrate region within the substrate, laterally separated from the first doped substrate region, and being biased to a power supply voltage potential via a second metal region, the second doped substrate region having a doped portion of a second conductivity type which is different from the first conductivity type; a gate oxide layer formed overlying the substrate; and a first conductive region formed overlying the first doped substrate region and separated from the first doped substrate region by the gate oxide layer, the first conducive region being biased to the power supply voltage potential which creates an inversion region in the doped portion of the first conductivity type; and a second conductive region formed overlying the second doped substrate region and separated from the second doped substrate region by the gate oxide layer, the second conductive region being biased to the ground voltage potential which creates an inversion region in the doped portion of the second conductivity type.

Claim 3

The integrated circuit standard cell of claim 1 wherein the first conductive region and the first doped substrate region are each an electrode of a capacitor which reduces noise on a power supply conductor.

Claim 4

The integrated circuit standard cell of claim 1 wherein the second conductive region and the second doped substrate region are each an electrode of a capacitor which reduces noise on a ground conductor.

Claim 5

The integrated circuit standard cell of claim 1 wherein the gate oxide layer has a thickness within a range of 50 angstroms to 250 angstroms.

Claim 6

A semiconductor device comprising: a substrate having a surface; a first doped region formed within the substrate, the first doped region being a P doped region which is used to support formation of N type source and drain regions within the P doped region, the P doped region forming an N-channel region a second doped region formed within the substrate, the second doped region being an N doped region which is used to support formation of P type source and drain regions within the N doped region, the N doped region forming a P-channel region; a dielectric layer formed overlying the surface of the substrate; a first conductive region formed overlying the dielectric layer and overlying the N-channel region; a second conductive region formed overlying the dielectric layer, laterally separated from the first conductive region, and overlying the P-channel region; a first metal conductor for providing a power supply potential, the first metal conductor being coupled to the first conductive region to form a capacitor between the first conductive region and the first doped region; and a second metal conductor for supplying a ground potential, the second metal conductor being coupled to the second conductive region to form a capacitor between the second conductive region and the second doped region.

Claim 7

A semiconductor device comprising: a substrate having a surface; a first doped region formed within the substrate, the first doped region being a P doped region which is used to support formation of N type source and drain regions within the P doped region, the P doped region forming an N-channel region a second doped region formed within the substrate, the second doped region being an N doped region which is used to support formation of P type source and drain regions within the N doped region, the N doped region forming a P-channel region; a dielectric layer formed overlying the surface of the substrate; a first conductive region formed overlying the dielectric layer and overlying the N-channel region; a second conductive region formed overlying the dielectric layer, laterally separated from the first conductive region, and overlying the P-channel region; a first metal conductor for providing a power supply potential, the first metal conductor being coupled to the first conductive region to form a capacitor between the first conductive region and the first doped region; and a second metal conductor for supplying a ground potential, the second metal conductor being coupled to the second conductive region to form a capacitor between the second conductive region and the second doped region.

Claim 8

The semiconductor device of claim 5 wherein the first conductive region is used as a capacitor electrode to reduce signal noise in the first metal conductor.

Claim 9

The semiconductor device of claim 5 wherein the second conductive region is used as a capacitor electrode to reduce signal noise in the second metal conductor.

Claim 10

The semiconductor device of claim 5 wherein a standard cell which contains at least one logic device is placed laterally adjacent the semiconductor device wherein the standard cell is coupled to the first and second metal conductors.

Claim 11

A standard cell circuit comprising: a P channel transistor having a drain electrode electrically coupled to a source electrode, a gate electrode overlying a channel region which is inverted to form an inversion region within a substrate, the inversion region being biased to a ground potential and the gate electrode being biased to a power supply potential; and an N channel transistor having a drain electrode electrically coupled to a source electrode, a gate electrode overlying a channel region which is inverted to form an inversion region within a substrate, the inversion region being biased to the power supply potential and the gate electrode being biased to the ground potential, the N channel transistor being laterally adjacent the P channel transistor.

Claim 12

A standard cell circuit comprising: a P channel transistor having a drain electrode electrically coupled to a source electrode, a gate electrode overlying a channel region which is inverted to form an inversion region within a substrate, the inversion region being biased to a ground potential and the gate electrode being biased to a power supply potential; and an N channel transistor having a drain electrode electrically coupled to a source electrode, a gate electrode overlying a channel region which is inverted to form an inversion region within a substrate, the inversion region being biased to the power supply potential and the gate electrode being biased to the ground potential, the N channel transistor being laterally adjacent the P channel transistor.

Claim 13

The standard cell circuit of claim 9 wherein another standard cell circuit which comprises at least one logic device is formed laterally adjacent the standard cell circuit and is coupled to both the ground and power supply potentials.

Claim 14

The standard cell circuit of claim 9 wherein both the ground and power supply potentials have reduced electrical noise due to both the P channel transistor and the N channel transistor functioning as capacitors.

Claim 15

A standard cell layout comprising: a substrate; a dielectric layer formed overlying the substrate; a power supply conductor overlying the dielectric layer; a ground conductor overlying the dielectric layer; a first active region defined within the substrate and being coupled to the power supply conductor through a first plurality of contact openings formed through the dielectric layer, the first active region being of a first conductivity type; a second active region defined within the substrate and being laterally adjacent the first active region, the second active region being coupled to the ground conductor through a second plurality of contact openings formed through the dielectric layer, the second active being of a second conductivity type which is different from the first conductivity type; a first conductive layer overlying the first active region, being separated form the first active region by a first gate dielectric region, and being coupled to the ground supply conductor through a third plurality of contact openings formed through the dielectric layer; and a second conductive layer overlying the second active region, being separated form the second active region by a second gate dielectric region, and being coupled to the power supply conductor through a fourth plurality of contact openings formed through the dielectric layer.

Claim 16

A standard cell layout comprising: a substrate; a dielectric layer formed overlying the substrate; a power supply conductor overlying the dielectric layer; a ground conductor overlying the dielectric layer; a first active region defined within the substrate and being coupled to the power supply conductor through a first plurality of contact openings formed through the dielectric layer, the first active region being of a first conductivity type; a second active region defined within the substrate and being laterally adjacent the first active region, the second active region being coupled to the ground conductor through a second plurality of contact openings formed through the dielectric layer, the second active being of a second conductivity type which is different from the first conductivity type; a first conductive layer overlying the first active region, being separated form the first active region by a first gate dielectric region, and being coupled to the ground supply conductor through a third plurality of contact openings formed through the dielectric layer; and a second conductive layer overlying the second active region, being separated form the second active region by a second gate dielectric region, and being coupled to the power supply conductor through a fourth plurality of contact openings formed through the dielectric layer.

Claim 17

The standard cell layout of claim 12 wherein the first conductive layer is coupled via metal to a portion of the substrate so that the first conductive layer will not electrically charge to a charge level wherein the first gate dielectric region is adversely affected.

Claim 18

The standard cell layout of claim 12 wherein the second conductive layer is coupled via metal to a portion of the substrate so that the second conductive layer will not electrically charge to a charge level wherein the second gate dielectric region is adversely affected.

Claim 19

The integrated circuit standard cell of claim 1 wherein the first doped substrate region has both a P type substrate tie region and an N type diffusion region where both the P type substrate tie and the N type diffusion region are coupled to the first metal region.

Claim 20

The integrated circuit standard cell of claim 1 wherein the second doped substrate region has both an N well region and a P type diffusion region within the N well region where the P type diffusion region is coupled to the second metal region.

Claim 21

The semiconductor device of claim 5 wherein replicas of the semiconductor device are automatically placed by a place and route tool into a plurality of unused substrate areas on the surface of an integrated circuit die, wherein the plurality of unused substrate areas are areas not occupied by other standard logic cells, whereby the plurality of unused areas are coupled for a purpose of reducing power supply and ground supply noise via on-chip capacitors.

Claim 22

A semiconductor device comprising: a substrate having a surface; a first doped region formed within the substrate which is an N type transistor region; a second doped region formed within the substrate which is a P type transistor region; a dielectric layer formed overlying the surface of the substrate; a first conductive region formed overlying the dielectric layer and in close proximity to the first doped region; a second conductive region formed overlying the dielectric layer, laterally separated from the first conductive region, and in close proximity to the second doped region; a first metal conductor for providing a power supply potential, the first metal conductor being coupled to the first conductive region to form a capacitor between the first conductive region and the first doped region; a second metal conductor for supplying a ground potential, the second metal conductor being coupled to the second conductive region to form a capacitor between the second conductive region and the second doped region; and wherein replicas of the semiconductor device are automatically placed by a place and route tool into a plurality of unused substrate areas on the surface of an integrated circuit die, wherein the plurality of unused substrate areas are areas not occupied by other standard logic cells, whereby the plurality of unused areas are coupled for a purpose of reducing power supply and ground supply noise via on-chip capacitors.

Claim 23

A semiconductor device comprising: a substrate having a surface; a first doped region formed within the substrate which is an N type transistor region; a second doped region formed within the substrate which is a P type transistor region; a dielectric layer formed overlying the surface of the substrate; a first conductive region formed overlying the dielectric layer and in close proximity to the first doped region; a second conductive region formed overlying the dielectric layer, laterally separated from the first conductive region, and in close proximity to the second doped region; a first metal conductor for providing a power supply potential, the first metal conductor being coupled to the first conductive region to form a capacitor between the first conductive region and the first doped region; a second metal conductor for supplying a ground potential, the second metal conductor being coupled to the second conductive region to form a capacitor between the second conductive region and the second doped region; and wherein replicas of the semiconductor device are automatically placed by a place and route tool into a plurality of unused substrate areas on the surface of an integrated circuit die, wherein the plurality of unused substrate areas are areas not occupied by other standard logic cells, whereby the plurality of unused areas are coupled for a purpose of reducing power supply and ground supply noise via on-chip capacitors.