Stable high voltage semiconductor device structure

Claim 2

A power device comprising: a semiconductor substrate comprising a top surface with an active region, a guard ring region, and a peripheral region, said active region including a junction region; a plurality of guard rings formed into said semiconductor substrate in said guard ring region, said guard ring region being between said active region and said peripheral region, said plurality of guard rings comprising a first guard ring nearest to said junction region and a last guard ring nearest to said peripheral region; a dielectric layer overlying said top surface and having portions between each of said plurality of guard rings, said dielectric layer having a portion between said junction region and said first guard ring, said dielectric layer having a portion between said last guard ring and said peripheral region; and a field plate layer, said field plate layer comprising portions each overlying each of said dielectric layer portions between each of said plurality of guard rings, said field plate layer having a portion overlying said dielectric layer portion between said junction region and said first guard ring, and said field plate layer having a portion overlying said dielectric layer portion between said last guard ring and said peripheral region; wherein at least one of said portions of said field plates being a floating plate structure to provide a more uniform distribution of an electric field underlying said floating plate structure.

Claim 3

The device of claim 1 further comprising a contact layer formed overlying a portion of said junction region and a portion of said field plate layer formed overlying said dielectric layer portion between said junction region and said first guard ring.

Claim 4

The device of claim 1 further comprising a contact layer formed overlying a portion said last guard ring and a portion of said field plate layer overlying said dielectric layer portion between said last guard ring and said peripheral region.

Claim 5

The device of claim 1 further comprising an insulating layer overlying said guard rings and field plate layer.

Claim 6

The device of claim 1 wherein each of said guard rings are substantially parallel to each other.

Claim 7

The device of claim 1 wherein said field plate layer comprises polysilicon.

Claim 8

The device of claim 1 wherein each of said guard rings comprise P type/P+ type diffusions.

Claim 9

The device of claim 7 wherein said P type impurity is at a concentration ranging from about 10 14 atoms/μm 3 to about 10 18 atoms/μm 3 , and said P+ type impurity is at a concentration ranging from about 10 15 atoms/μm 3 to about 10 19 atoms/μm 3 .

Claim 10

The device of claim 1 wherein said peripheral region includes a scribe region.

Claim 11

The device of claim 1 wherein said semiconductor substrate comprises an N+ type layer and an N- type layer overlying said N+ type layer.

Claim 12

The device of claim 1 wherein said field plate layer overlying each of said dielectric layer portions between each of said plurality of guard rings comprises a plurality of field plates, said plurality of field plates being separated from each other.

Claim 13

A power device comprising: a semiconductor substrate comprising a top surface with an active region, a guard ring region, and a peripheral region, said active region including a junction region; a plurality of guard rings formed into said semiconductor substrate in said guard ring region, said guard ring region being between said active region and said peripheral region, said plurality of guard rings comprising a first guard ring nearest to said junction region and a last guard ring nearest to said peripheral region; a dielectric layer overlying said top surface and having portions between each of said plurality of guard rings, said dielectric layer having a portion between said junction region and said first guard ring, said dielectric layer having a portion between said last guard ring and said peripheral region; and a field plate layer, said field plate layer comprising a plurality of field plates overlying each of said dielectric layer portions between each of said plurality of guard rings, said field plate layer overlying said dielectric layer portion between said junction region and said first guard ring, and said field plate layer comprising a plurality of field plates overlying said dielectric layer portion between said last guard ring and said peripheral region.

Claim 14

A power device comprising: a semiconductor substrate comprising a top surface with an active region, a guard ring region, and a peripheral region, said active region including a junction region; a plurality of guard rings formed into said semiconductor substrate in said guard ring region, said guard ring region being between said active region and said peripheral region, said plurality of guard rings comprising a first guard ring nearest to said junction region and a last guard ring nearest to said peripheral region; a dielectric layer overlying said top surface and having portions between each of said plurality of guard rings, said dielectric layer having a portion between said junction region and said first guard ring, said dielectric layer having a portion between said last guard ring and said peripheral region; and a field plate layer, said field plate layer comprising a plurality of field plates overlying each of said dielectric layer portions between each of said plurality of guard rings, said field plate layer overlying said dielectric layer portion between said junction region and said first guard ring, and said field plate layer comprising a plurality of field plates overlying said dielectric layer portion between said last guard ring and said peripheral region.

Claim 15

The device of claim 12 wherein at least one of said field plates overlying each of said dielectric layer portions between each of said plurality of guard rings is coupled to one of said plurality of guard rings.

Claim 16

The device of claim 12 wherein said field plate layer overlying said dielectric layer portion between said junction region and said first guard ring is coupled to said junction region.

Claim 17

The device of claim 12 wherein at least one of said plurality of field plates overlying said dielectric layer portion between said last guard ring and said peripheral region is coupled to said last guard ring.

Claim 18

The device of claim 12 wherein at least one of said plurality of field plates overlying said dielectric layer portion between said last guard ring and said peripheral region is coupled to said peripheral region.

Claim 19

The device of claim 12 wherein said peripheral region is a scribe region.

Claim 20

The device of claim 12 wherein said plurality of field plates overlying said dielectric layer portion between said last guard ring and said peripheral region is separated from each other by a distance less than about 4 μm.

Claim 21

The device of claim 12 wherein a plurality of said field plates overlying each of said dielectric layer portions between each of said plurality of guard rings is separated from each other by a distance less than about 4 μm.

Claim 22

A power device comprising: a semiconductor substrate comprising a top surface with an active region, a guard ring region, and a peripheral region, said active region including a junction region; a plurality of guard rings formed into said semiconductor substrate in said guard ring region, said guard ring region being between said active region and said peripheral region, said plurality of guard rings comprising a first guard ring nearest to said junction region and a last guard ring nearest to said peripheral region; a dielectric layer overlying said top surface and having portions between each of said plurality of guard rings, said dielectric layer having a portion between said junction region and said first guard ring, said dielectric layer having a portion between said last guard ring and said peripheral region; and a field plate layer, said field plate layer overlying each of said dielectric layer portions between each of said plurality of guard rings, said field plate layer overlying said dielectric layer portion between said junction region and said first guard ring, and said field plate layer overlying said dielectric layer portion between said last guard ring and said peripheral region, said field plate layer overlying said dielectric layer portion between said last guard ring and said peripheral region comprise a plurality of field plates, said plurality of field plates comprising a first field plate and a second field plate, said first field plate being separated from said second field plate.

Claim 23

A power device comprising: a semiconductor substrate comprising a top surface with an active region, a guard ring region, and a peripheral region, said active region including a junction region; a plurality of guard rings formed into said semiconductor substrate in said guard ring region, said guard ring region being between said active region and said peripheral region, said plurality of guard rings comprising a first guard ring nearest to said junction region and a last guard ring nearest to said peripheral region; a dielectric layer overlying said top surface and having portions between each of said plurality of guard rings, said dielectric layer having a portion between said junction region and said first guard ring, said dielectric layer having a portion between said last guard ring and said peripheral region; and a field plate layer, said field plate layer overlying each of said dielectric layer portions between each of said plurality of guard rings, said field plate layer overlying said dielectric layer portion between said junction region and said first guard ring, and said field plate layer overlying said dielectric layer portion between said last guard ring and said peripheral region, said field plate layer overlying said dielectric layer portion between said last guard ring and said peripheral region comprise a plurality of field plates, said plurality of field plates comprising a first field plate and a second field plate, said first field plate being separated from said second field plate.

Claim 24

The device of claim 20 further comprising a first contact formed overlying a portion said last guard ring and a portion of said first field plate and a second contact layer formed overlying a portion of said peripheral region and said second field plate.

Claim 25

The device of claim 21 wherein said plurality of field plates further comprises at least one field plate between said first field plate and said second field plate, said at least one field plate being separated from said first field plate and said second field plate.

Claim 26

The device of claim 22 further comprising a dielectric layer separating said at least one field plate from said first field plate and said second field plate.

Claim 27

The device of claim 23 wherein said dielectric layer includes a thickness ranging from about 0.05 μm to about 2.5 μm.