Method and circuit for detecting data collisions in communication network

Claim 2

A circuit for detecting data collisions in a communication network, comprising: a data transition detector receiving a Manchester encoded data signal, the data transition detector detecting a transition at the center of a bit cell of the Manchester encoded data signal and outputting a transition detecting signal of a certain pulse width and a high or low state; a delaying means for delaying a received clock signal having a cycle synchronized with the Manchester encoded data signal and outputting a delayed clock signal; and a data collision detector placed in an active mode in response to a data receiving status signal and shifting an output signal in accordance with the transition detecting signal upon clocking of the delayed clock signal; wherein the data collision detector comprises one or more shifting means for receiving the transition detecting signal from the data transition detector at a data input of the data collision detector and receiving the delayed clock signal from the delaying means at a clock input of the data collision detector, and outputting an output signal having a high or low state determined by the high or low state of the data input to the data input at a rising edge of the delayed clock signal.

Claim 3

The circuit of claim 1, wherein the data transition detector comprises: a delaying means for delaying the Manchester encoded data signal for a certain period of time; and a logic circuit for logic-processing the Manchester encoded data signal and the delayed data signal.

Claim 4

The circuit of claim 2, wherein the logic circuit comprises: a first NAND gate having two input terminals, a first input terminal of which receives the Manchester encoded data signal, and a second input terminal of which receives the output of the delaying means; a first inverter for inverting the Manchester encoded data signal and supplying the inverted data signal to the delaying means; a second inverter for inverting the output of the delaying means to generate an inverted output; a third inverter for inverting the Manchester encoded data signal to generate an inverted output; a second NAND gate receiving as inputs the outputs from the second and third inverters; and a third NAND gate for receiving outputs from the first and second NAND gates as inputs and outputting the transition detecting signal.

Claim 5

The circuit of claim 1, wherein the data collision detector comprises one or more flip-flops receiving the transition detecting signal from the data transition detector into a data input terminal, and receiving the delayed clock signal from the delayer into a clock input terminal, and outputting an output having the same status as the data input to the data input terminal at a rising edge of the delayed clock signal, and outputting a data collision signal through an output terminal of one of the flip-flops.

Claim 6

The circuit of claim 1, wherein the data collision detector comprises three D flip-flops connected in series and receiving the transition detecting signals from the data transition detector into a data input terminal, and receiving the delayed clock signal into a clock input terminal and outputting an output having the same status as the data input at a rising edge of the clock signal, and outputting a data collision signal through an output terminal; wherein the output terminal of a preceding stage of the D flip-flops is connected to an input terminal of a following stage of the D flip-flops, and the output terminal of a final stage outputs the data collision signal.

Claim 7

The circuit of claim 2, wherein the logic circuit comprises: a first NAND gate having two input terminals, a first input terminal of which receives the Manchester encoded data signal, and a second input terminal of which receives the output of the delaying means; a first inverter for inverting the Manchester encoded data signal and supplying the inverted data signal to the delaying means; a second inverter for inverting the output of the delaying means to generate an inverted output; a second NAND gate receiving as inputs the outputs from the first and second inverters; and a third NAND gate for receiving outputs from the first and second NAND gates as inputs and outputting the transition detecting signal.

Claim 10

The method of claim 7, where in the data collision signal is not output if at the time of outputting the data collision signal the encoded data signal is not being received.

Claim 11

The method of claim 7, wherein the step of forming the data transition detecting signal comprises the steps of delaying the encoded data signal for a certain time period to form a delayed data signal, and logically processing the delayed data signal and undelayed data signal, wherein the data transition detecting signal is generated by the logical processing upon an occurrence of a data transition of the encoded data signal.

Claim 12

The circuit of claim 1, further comprising a packet transmission network coupled to the data transition detector, wherein the data signal comprises packet transmission data.

Claim 13

The method of claim 7, wherein the step of outputting the data collision signal is carried out in such a manner that, if the data transition detecting signal does not exist at a data input of a first flip-flop at a rising edge of the delayed clock signal, then an output of the first flip-flop is shifted to a low state, an output of a second flip-flop is shifted to a low state at a second rising edge of the delayed clock, and an output of a third flip-flop is shifted to a low state at a third rising edge of the delayed clock, wherein the output of the third flip-flop is delayed three cycles of the delayed clock signal to recognize occurrence of a data collision.

Claim 14

The method of claim 11, wherein if the data signal does not exist before the rising edge of the third clock pulse, then an occurrence of a data collision is not recognized.

Claim 15

The method of claim 9, wherein the clock signal delaying time is about 1/2 of the data signal delaying time.

Claim 16

A circuit for detecting data collisions in a communication network, comprising: a data transition detector receiving a data signal, the data transition detector detecting a transition at a center portion of a bit cell of the data signal and outputting a transition detecting signal of a certain pulse width; a delayer delaying a received clock signal having a cycle synchronized with the data signal and outputting delayed clock signal; and a data collision detector placed in an active mode in response to a data receiving status signal and shifting an output signal in accordance with the transition detecting signal upon clocking of the delayed clock signal; wherein the data transition detector comprises: a delaying means for delaying the data signal for a certain period of time; and a logic circuit for logic-processing the data signal and the delayed data signal; wherein the logic circuit comprises: a first NAND gate having two input terminal of which receives the data signal, and a second input terminal of which receives the output of the delaying means; a first inverter for inverting the data signal and supplying the inverted data signal to the delaying means; a second inverter for inverting the output of the delaying means to generate an inverted output; a third inverter for inverting the data signal to generate an inverted output; a second NAND gate receiving as inputs the outputs from the second and third inverters; and a third NAND gate for receiving outputs from the first and second NAND gates as inputs and outputting the transition detecting signal.

Claim 17

A circuit for detecting data collisions in a communication network, comprising: a data transition detector receiving a data signal, the data transition detector detecting a transition at a center portion of a bit cell of the data signal and outputting a transition detecting signal of a certain pulse width; a delayer delaying a received clock signal having a cycle synchronized with the data signal and outputting delayed clock signal; and a data collision detector placed in an active mode in response to a data receiving status signal and shifting an output signal in accordance with the transition detecting signal upon clocking of the delayed clock signal; wherein the data transition detector comprises: a delaying means for delaying the data signal for a certain period of time; and a logic circuit for logic-processing the data signal and the delayed data signal; wherein the logic circuit comprises: a first NAND gate having two input terminal of which receives the data signal, and a second input terminal of which receives the output of the delaying means; a first inverter for inverting the data signal and supplying the inverted data signal to the delaying means; a second inverter for inverting the output of the delaying means to generate an inverted output; a third inverter for inverting the data signal to generate an inverted output; a second NAND gate receiving as inputs the outputs from the second and third inverters; and a third NAND gate for receiving outputs from the first and second NAND gates as inputs and outputting the transition detecting signal.

Claim 18

The circuit of claim 14, wherein the data signal comprises a Manchester encoded data signal.

Claim 19

The circuit of claim 14, further comprising a packet transmission network coupled to the data transition detector, wherein the data signal comprises packet transmission data.

Claim 20

A circuit for detecting data collisions in a communication network, comprising: a data transition detector receiving a data signal, the data transition detector detecting a transition at a center portion of a bit cell of the data signal and outputting a transition detecting signal of a certain pulse width; a delayer delaying a received clock signal having a cycle synchronized with the data signal and outputting a delayed clock signal; and a data collision detector placed in an active mode in response to a data receiving status signal and shifting an output signal in accordance with the transition detecting signal upon clocking of the delayed clock signal; wherein the data collision detector comprises one or more flip-flops receiving the transition detecting signal from the data transition detector into a data input terminal, and receiving the delayed clock signal from the delayer into a clock input terminal, and outputting an output having the same status as the data input to the data input terminal at a rising edge of the delayed clock signal, and outputting a data collision signal through an output terminal of one of the flip-flops.

Claim 21

A circuit for detecting data collisions in a communication network, comprising: a data transition detector receiving a data signal, the data transition detector detecting a transition at a center portion of a bit cell of the data signal and outputting a transition detecting signal of a certain pulse width; a delayer delaying a received clock signal having a cycle synchronized with the data signal and outputting a delayed clock signal; and a data collision detector placed in an active mode in response to a data receiving status signal and shifting an output signal in accordance with the transition detecting signal upon clocking of the delayed clock signal; wherein the data collision detector comprises one or more flip-flops receiving the transition detecting signal from the data transition detector into a data input terminal, and receiving the delayed clock signal from the delayer into a clock input terminal, and outputting an output having the same status as the data input to the data input terminal at a rising edge of the delayed clock signal, and outputting a data collision signal through an output terminal of one of the flip-flops.

Claim 22

The circuit of claim 17, wherein the data signal comprises a Manchester encoded data signal.

Claim 23

The circuit of claim 17, further comprising a packet transmission network coupled to the data transition detector, wherein the data signal comprises packet transmission data.

Claim 24

A circuit for detecting data collisions in a communication network, comprising: a data transition detector receiving a data signal, the data transition detector detecting a transition at a center portion of a bit cell of the data signal and outputting a transition detecting signal of a certain pulse width; a delayer delaying a received clock signal having a cycle synchronized with the data signal and outputting a delayed clock signal; and a data collision detector placed in an active mode in response to a data receiving status signal and shifting an output signal in accordance with the transition detecting signal upon clocking of the delayed clock signal; wherein the data collision detector comprises a plurality of flip-flops connected in series and receiving the transition detecting signals from the data transition detector into a data input terminal, and receiving the delayed clock signal into a clock input terminal and outputting an output having the same status as the data input at a rising edge of the clock signal, and outputting a data collision signal through an output terminal; wherein the output terminal of a preceding stage of the flip-flops is connected to an input terminal of a following stage of the flip-flops, and the output terminal of a final stage outputs the data collision signal.

Claim 25

A circuit for detecting data collisions in a communication network, comprising: a data transition detector receiving a data signal, the data transition detector detecting a transition at a center portion of a bit cell of the data signal and outputting a transition detecting signal of a certain pulse width; a delayer delaying a received clock signal having a cycle synchronized with the data signal and outputting a delayed clock signal; and a data collision detector placed in an active mode in response to a data receiving status signal and shifting an output signal in accordance with the transition detecting signal upon clocking of the delayed clock signal; wherein the data collision detector comprises a plurality of flip-flops connected in series and receiving the transition detecting signals from the data transition detector into a data input terminal, and receiving the delayed clock signal into a clock input terminal and outputting an output having the same status as the data input at a rising edge of the clock signal, and outputting a data collision signal through an output terminal; wherein the output terminal of a preceding stage of the flip-flops is connected to an input terminal of a following stage of the flip-flops, and the output terminal of a final stage outputs the data collision signal.

Claim 26

The circuit of claim 20, wherein the data signal comprises a Manchester encoded data signal.

Claim 27

The circuit of claim 20, further comprising a packet transmission network coupled to the data transition detector, wherein the data signal comprises packet transmission data.

Claim 28

A circuit for detecting data collisions in a communication network, comprising: a data transition detector receiving a data signal, the data transition detector detecting a transition at a center portion of a bit cell of the data signal and outputting a transition detecting signal of a certain pulse width; a delayer delaying a received clock signal having a cycle synchronized with the data signal and outputting a delayed clock signal; and a data collision detector .placed in an active mode in response to a data receiving status signal and shifting an output signal in accordance with the transition detecting signal upon clocking of the delayed clock signal; wherein the data transition detector comprises: a delaying means for delaying the data signal for a certain period of time; and a logic circuit for logic-processing the data signal and the delayed data signal; wherein the logic circuit comprises: a first NAND gate having two input terminals, a first input terminal of which receives the data signal, and a second input terminal of which receives the output of the delaying means; a first inverter for inverting the data signal and supplying the inverted data signal to the delaying means; a second inverter for inverting the output of the delaying means to generate an inverted output; a second NAND gate receiving as inputs the outputs from the first and second inverters; and a third NAND gate for receiving outputs from the first and second NAND gates as inputs and outputting the transition detecting signal.

Claim 29

A circuit for detecting data collisions in a communication network, comprising: a data transition detector receiving a data signal, the data transition detector detecting a transition at a center portion of a bit cell of the data signal and outputting a transition detecting signal of a certain pulse width; a delayer delaying a received clock signal having a cycle synchronized with the data signal and outputting a delayed clock signal; and a data collision detector .placed in an active mode in response to a data receiving status signal and shifting an output signal in accordance with the transition detecting signal upon clocking of the delayed clock signal; wherein the data transition detector comprises: a delaying means for delaying the data signal for a certain period of time; and a logic circuit for logic-processing the data signal and the delayed data signal; wherein the logic circuit comprises: a first NAND gate having two input terminals, a first input terminal of which receives the data signal, and a second input terminal of which receives the output of the delaying means; a first inverter for inverting the data signal and supplying the inverted data signal to the delaying means; a second inverter for inverting the output of the delaying means to generate an inverted output; a second NAND gate receiving as inputs the outputs from the first and second inverters; and a third NAND gate for receiving outputs from the first and second NAND gates as inputs and outputting the transition detecting signal.

Claim 30

The circuit of claim 23, wherein the data signal comprises a Manchester encoded data signal.

Claim 31

The circuit of claim 23, further comprising a packet transmission network coupled to the data transition detector, wherein the data signal comprises packet transmission data.

Claim 34

The method of claim 26, wherein the data signal comprises Manchester encoded data.

Claim 35

The method of claim 26, wherein if the data signal does not exist before the rising edge of the third clock pulse, then an occurrence of a data collision is not recognized.

Claim 38

The method of claim 29, wherein the data signal comprises Manchester encoded data.