Method for fabricating semiconductor devices having bit lines and storage node contacts

Claim 1

A method of manufacturing a semiconductor device comprising the steps of: depositing a first insulating layer on a semiconductor substrate having active electrodes of source, drain and gate; forming a conductive layer pattern to provide a bit line pattern on said first insulating layer; depositing a second insulating layer that completely covers said first insulating layer and bit line pattern; depositing sequentially a third insulating layer and a fourth insulating layer which have different etch rates on the second insulating layer; masking and etching said fourth and third insulating layers to form T-shaped patterns in cross-sectional view, wherein the fourth insulating layer corresponds to a head portion of the T-shaped pattern, and the third insulating layer corresponds to a leg portion of the T-shaped pattern, wherein one of said T-shaped, patterns forms a bit line contact and another one of said T-shaped patterns forms a storage node contact; forming polysilicon spacers at a sidewall of the T-shaped patterns; depositing a fifth insulating layer on an entire surface of a resultant structure including the T-shaped patterns; forming first photoresist mask patterns for forming bit line contact holes on said fifth insulating layer over said one of said T-shaped patterns; etching portions of said fifth insulating layer and said one of said T-shaped insulating layer pattern using said first photoresist mask, etching a portion of said second insulating layer by using a polysilicon spacer as an etch barrier, etching the bit line pattern using the etched second insulating layer as an etch barrier and etching the first insulating layer using said bit line as an etch barrier, thereby forming a bit line contact hole; depositing and patterning a conducting material on an entire surface of the fifth insulating layer including said bit line contact hole; depositing a sixth insulating layer on an entire surface of said fifth insulating layer and said conducting material pattern; forming a second photoresist mask pattern for forming a storage node contact hole on said sixth insulating layer over said another one of said T-shaped patterns; etching portions of said sixth and fifth insulating layers and T-shaped pattern using said second photoresist mask, etching portions of said second insulating layer and said first insulating layer using said polysilicon spacer which acts as an etch barrier, thereby forming a storage node contact hole.

Claim 2

A method of manufacturing a semiconductor device comprising the steps of: depositing a first insulating layer on a semiconductor substrate having active electrodes of source, drain and gate; forming a conductive layer pattern to provide a bit line pattern on said first insulating layer; depositing a second insulating layer that completely covers said first insulating layer and bit line pattern; depositing sequentially a third insulating layer and a fourth insulating layer which have different etch rates on the second insulating layer; masking and etching said fourth and third insulating layers to form T-shaped patterns in cross-sectional view, wherein the fourth insulating layer corresponds to a head portion of the T-shaped pattern, and the third insulating layer corresponds to a leg portion of the T-shaped pattern, wherein one of said T-shaped, patterns forms a bit line contact and another one of said T-shaped patterns forms a storage node contact; forming polysilicon spacers at a sidewall of the T-shaped patterns; depositing a fifth insulating layer on an entire surface of a resultant structure including the T-shaped patterns; forming first photoresist mask patterns for forming bit line contact holes on said fifth insulating layer over said one of said T-shaped patterns; etching portions of said fifth insulating layer and said one of said T-shaped insulating layer pattern using said first photoresist mask, etching a portion of said second insulating layer by using a polysilicon spacer as an etch barrier, etching the bit line pattern using the etched second insulating layer as an etch barrier and etching the first insulating layer using said bit line as an etch barrier, thereby forming a bit line contact hole; depositing and patterning a conducting material on an entire surface of the fifth insulating layer including said bit line contact hole; depositing a sixth insulating layer on an entire surface of said fifth insulating layer and said conducting material pattern; forming a second photoresist mask pattern for forming a storage node contact hole on said sixth insulating layer over said another one of said T-shaped patterns; etching portions of said sixth and fifth insulating layers and T-shaped pattern using said second photoresist mask, etching portions of said second insulating layer and said first insulating layer using said polysilicon spacer which acts as an etch barrier, thereby forming a storage node contact hole.