US5625563A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and system for reducing the number of connections between a plurality of semiconductor devices
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1995-01-09
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Granted: 1997-04-29
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Expires: 2015-01-09
Abstract
Abstract Serial high speed interconnect devices are integrated with semiconductor devices to reduce the number of input-output pins required for communications and control between a plurality of semiconductor devices. The serial high speed interconnect devices transfer the data serially at a rate fast enough to replace large parallel data and address buses that require one conductive path per bit of data. Eliminating large parallel data and address buses allows the integrated circuit assembly containing the semiconductor device to be smaller, simpler and lower in cost. The subsequent reduction in the size of the integrated circuits improves the layout density of electronic systems and reduces crosstalk and other undesirable signal transfer anomalies. The serial high speed interconnection devices are implemented with a low cost serial interface logic technology that may be easily implemented on a semiconductor die in conjunction with the main logic circuits.
Inventors
- 👤 Michael D. Rostoker
- 👤 Scott A. Macomber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:42
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/066; H; H04; H04L; H04L12/00; H04L12/28
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
221 words
A system for reducing the number of signal connections between a plurality of semiconductor device assemblies, comprising: a first integrated circuit assembly containing a first semiconductor device and a plurality of first signal links, said first semiconductor device connected to said plurality of first signal links and said plurality of first signal links connected to a plurality of first signal connections on said first integrated circuit assembly; a second integrated circuit assembly containing a second semiconductor device and a plurality of second signal links, said second semiconductor device connected to said plurality of second signal links and said plurality of second signal links connected to a plurality of second signal connections on said second integrated circuit assembly; said plurality of first and second signal connections connected together by a plurality of signal interconnections, wherein digital data is transferred between said first and second integrated circuit assemblies over said plurality of signal interconnections; and a plurality of first and second signal link enables, each of said plurality of first and second enables activates each of said plurality of first and second signal links, respectively, wherein the enabled ones of said first and second signal links transfer high speed serial data and the disabled other ones of said first and second signal links transfers parallel data at one bit per disabled signal link.
Claim 2
Independent Claim
221 words
A system for reducing the number of signal connections between a plurality of semiconductor device assemblies, comprising: a first integrated circuit assembly containing a first semiconductor device and a plurality of first signal links, said first semiconductor device connected to said plurality of first signal links and said plurality of first signal links connected to a plurality of first signal connections on said first integrated circuit assembly; a second integrated circuit assembly containing a second semiconductor device and a plurality of second signal links, said second semiconductor device connected to said plurality of second signal links and said plurality of second signal links connected to a plurality of second signal connections on said second integrated circuit assembly; said plurality of first and second signal connections connected together by a plurality of signal interconnections, wherein digital data is transferred between said first and second integrated circuit assemblies over said plurality of signal interconnections; and a plurality of first and second signal link enables, each of said plurality of first and second enables activates each of said plurality of first and second signal links, respectively, wherein the enabled ones of said first and second signal links transfer high speed serial data and the disabled other ones of said first and second signal links transfers parallel data at one bit per disabled signal link.
Claim 3
Dependent Claim
15 words
The system of claim 1, wherein said signal interconnection is a constant impedance strip line.
Claim 4
Dependent Claim
13 words
The system of claim 1, wherein said signal interconnection is a coaxial cable.
Claim 5
Dependent Claim
14 words
The system of claim 1, wherein said signal interconnection is a twisted wire pair.
Claim 6
Dependent Claim
97 words
A semiconductor device assembly having a reduced number of signal connections, comprising: a semiconductor device; at least one signal link connected to said semiconductor device; at least one signal link enable connected to said at least one signal link for enabling and disabling said at least one signal link, wherein said at least one signal link when enabled is capable of transferring high speed digital serial information and when disabled is capable of transferring only a single bit of parallel information; and said at least one signal link connected to at least one high speed signal interconnection.
Claim 7
Dependent Claim
97 words
A semiconductor device assembly having a reduced number of signal connections, comprising: a semiconductor device; at least one signal link connected to said semiconductor device; at least one signal link enable connected to said at least one signal link for enabling and disabling said at least one signal link, wherein said at least one signal link when enabled is capable of transferring high speed digital serial information and when disabled is capable of transferring only a single bit of parallel information; and said at least one signal link connected to at least one high speed signal interconnection.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-28 | 2000-10-28 | 2001-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-28 | 2004-10-28 | 2005-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-28 | 2008-10-28 | 2009-04-29 | $7700.00 | Window Closed / Lapsed |